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A new concept of vertically integrated pattern recognition associative memory

Description: Hardware-based pattern recognition for fast triggering on particle tracks has been successfully used in high-energy physics experiments for some time. The CDF Silicon Vertex Trigger (SVT) at the Fermilab Tevatron is an excellent example. The method used there, developed in the 1990's, is based on algorithms that use a massively parallel associative memory architecture to identify patterns efficiently at high speed. However, due to much higher occupancy and event rates at the LHC, and the fact t… more
Date: November 1, 2011
Creator: Liu, Ted; Hoff, Jim; Deptuch, Grzegorz & Yarema, Ray
Item Type: Refine your search to only Article
Partner: UNT Libraries Government Documents Department
open access

Proposal for the development of 3D Vertically Integrated Pattern Recognition Associative Memory (VIPRAM)

Description: Future particle physics experiments looking for rare processes will have no choice but to address the demanding challenges of fast pattern recognition in triggering as detector hit density becomes significantly higher due to the high luminosity required to produce the rare process. The authors propose to develop a 3D Vertically Integrated Pattern Recognition Associative Memory (VIPRAM) chip for HEP applications, to advance the state-of-the-art for pattern recognition and track reconstruction fo… more
Date: October 1, 2010
Creator: Deptuch, Gregory; Hoff, Jim; Kwan, Simon; Lipton, Ron; Liu, Ted; Ramberg, Erik et al.
Item Type: Refine your search to only Report
Partner: UNT Libraries Government Documents Department
open access

3D design activities at Fermilab: Opportunities for physics

Description: Fermilab began exploring the technologies for vertically integrated circuits (also commonly known as 3D circuits) in 2006. These technologies include through silicon vias (TSV), circuit thinning, and bonding techniques to replace conventional bump bonds. Since then, the interest within the High Energy Physics community has grown considerably. This paper will present an overview of the activities at Fermilab over the last 3 years which have helped spark this interest.
Date: January 1, 2009
Creator: Yarema, Raymond; Deptuch, Grezgorz; Hoff, Jim; Shenai, Alpana; Trimpl, Marcel; Zimmerman, Tom et al.
Item Type: Refine your search to only Article
Partner: UNT Libraries Government Documents Department
open access

Fermilab silicon strip readout chip for BTev

Description: A chip has been developed for reading out the silicon strip detectors in the new BTeV colliding beam experiment at Fermilab. The chip has been designed in a 0.25 {micro}m CMOS technology for high radiation tolerance. Numerous programmable features have been added to the chip, such as setup for operation at different beam crossing intervals. A full size chip has been fabricated and successfully tested. The design philosophy, circuit features, and test results are presented in this paper.
Date: May 1, 2005
Creator: Yarema, Raymond; Hoff, Jim; Mekkaoui, Abderrezak; Manghisoni, Massimo; Re, Valerio; Angeleri, Valentina et al.
Item Type: Refine your search to only Article
Partner: UNT Libraries Government Documents Department
open access

FPIX core architecture and the preFPIX2 chip: Architecture and simulation

Description: preFPIX2 is a developmental step in the evolution of the final BTeV pixel architecture. It is a smaller version of a fully functional FPIX Core. It is a necessary step between FPIX1 and FPIX2 mostly for monetary reasons. Both FPIX1 and FPIX2 must be bump bonded to 18 x 160 arrays of ATLAS pixel detectors. Therefore, since each pixel is 50 {micro}m by 400 {micro}m, each FPIX chip cannot possibly be smaller than 7.2 mm by 8 mm. Since such a large chip is expensive, the collaborators are only bein… more
Date: July 1, 2000
Creator: Hoff, Jim & Mekkaoui, Abder
Item Type: Refine your search to only Report
Partner: UNT Libraries Government Documents Department
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