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Charge Collection Studies on Integrated Circuit Test Structures using Heavy-Ion Microbeams and MEDICI Simulation Calculations

Description: Ion induced charge collection dynamics within Integrated Circuits (ICs) is important due to the presence of ionizing radiation in the IC environment. As the charge signals defining data states are reduced by voltage and area scaling, the semiconductor device will naturally have a higher susceptibility to ionizing radiation induced effects. The ionizing radiation can lead to the undesired generation and migration of charge within an IC. This can alter, for example, the memory state of a bit, and thereby produce what is called a "soft" error, or Single Event Upset (SEU). Therefore, the response of ICs to natural radiation is of great concern for the reliability of future devices. Immunity to soft errors is listed as a requirement in the 1997 National Technology Roadmap for Semiconductors prepared by the Semiconductor Industry Association in the United States. To design more robust devices, it is essential to create and test accurate models of induced charge collection and transport in semiconductor devices. A heavy ion microbeam produced by an accelerator is an ideal tool to study charge collection processes in ICs and to locate the weak nodes and structures for improvement through hardening design. In this dissertation, the Ion Beam Induced Charge Collection (IBICC) technique is utilized to simulate recoil effects of ions in ICs. These silicon or light ion recoils are usually produced by the elastic scattering or inelastic reactions between cosmic neutrons or protons and the lattice atoms in ICs. Specially designed test structures were experimentally studied, using microbeams produced at Sandia National Laboratories. A new technique, Diffusion Time Resolved IBICC, is first proposed in this work to measure the average arrival time of the diffused charge, which can be related to the first moment (or the average time) of the arrival carrier density at the junction. A 2D device simulation ...
Date: May 2000
Creator: Guo, Baonian
Partner: UNT Libraries

A Materials Approach to Silicon Wafer Level Contamination Issues from the Wet Clean Process

Description: Semiconductor devices are built using hyperpure silicon and very controlled levels of doping to create desired electrical properties. Contamination can alter these precisely controlled electrical properties that can render the device non-functional or unreliable. It is desirable to determine what impurities impact the device and control them. This study consists of four parts: a) determination of acceptable SCI (Standard Clean 1) bath contamination levels using VPD-DSE-GFAAS (Vapor Phase Decomposition Droplet Surface Etching Graphite Furnace Atomic Absorption Spectroscopy), b) copper deposition from various aqueous HF solutions, c) anion contamination from fluoropolymers used in chemical handling and d) metallic contamination from fluoropolymers and polyethylene used in chemical handling. A technique was developed for the determination of metals on a silicon wafer source at low levels. These levels were then correlated to contamination levels in a SCI bath. This correlation permits the determination of maximum permissible solution contaminant levels. Copper contamination is a concern for depositing on the wafer surface from hydrofluoric acid solutions. The relationship between copper concentration on the wafer surface and hydrofluoric acid concentration was determined. An inverse relationship exists and was explained by differences in diffusion rates between the differing copper species existing in aqueous hydrofluoric acid solutions. Finally, sources of contamination from materials used in chemical handling was studied. The predominant anion contamination from fluoropolymers was found to be fluorides. Metallic contamination from fluoropolymers and polyethylene was also studied. The primary metal contamination comes from the actual fabrication of the polymer and not from the polymer resin.
Date: December 1996
Creator: Hall, Lindsey H. (Lindsey Harrison)
Partner: UNT Libraries

An Efficient Hybrid Heuristic and Probabilistic Model for the Gate Matrix Layout Problem in VLSI Design

Description: In this thesis, the gate matrix layout problem in VLSI design is considered where the goal is to minimize the number of tracks required to layout a given circuit and a taxonomy of approaches to its solution is presented. An efficient hybrid heuristic is also proposed for this combinatorial optimization problem, which is based on the combination of probabilistic hill-climbing technique and greedy method. This heuristic is tested experimentally with respect to four existing algorithms. As test cases, five benchmark problems from the literature as well as randomly generated problem instances are considered. The experimental results show that the proposed hybrid algorithm, on the average, performs better than other heuristics in terms of the required computation time and/or the quality of solution. Due to the computation-intensive nature of the problem, an exact solution within reasonable time limits is impossible. So, it is difficult to judge the effectiveness of any heuristic in terms of the quality of solution (number of tracks required). A probabilistic model of the gate matrix layout problem that computes the expected number of tracks from the given input parameters, is useful to this respect. Such a probabilistic model is proposed in this thesis, and its performance is experimentally evaluated.
Date: August 1993
Creator: Bagchi, Tanuj
Partner: UNT Libraries

An Interactive Framework for Teaching Fundamentals of Digital Logic Design and VLSI Design

Description: Integrated Circuits (ICs) have a broad range of applications in healthcare, military, consumer electronics etc. The acronym VLSI stands for Very Large Scale Integration and is a process of making ICs by placing millions of transistors on a single chip. Because of advancements in VLSI design technologies, ICs are getting smaller, faster in speed and more efficient, making personal devices handy, and with more features. In this thesis work an interactive framework is designed in which the fundamental concepts of digital logic design and VLSI design such as logic gates, MOS transistors, combinational and sequential logic circuits, and memory are presented in a simple, interactive and user friendly way to create interest in students towards engineering fields, especially Electrical Engineering and Computer Engineering. Most of the concepts are explained in this framework by taking the examples which we see in our daily lives. Some of the critical design concerns such as power and performance are presented in an interactive way to make sure that students can understand these significant concepts in an easy and user friendly way.
Date: August 2014
Creator: Battina, Brahmasree
Partner: UNT Libraries

Microstructure studies of silicon-on-insulator for very large scale integrated circuit applications

Description: Silicon-on-insulator formed by high dose oxygen ion implantation and subsequent epitaxially grown silicon layers were studied and compared with silicon on sapphire materials. Czochralski grown, (100) silicon wafers were implanted with molecular oxygen ions, 0+2, to a total dose of 2.12 x 10^18 0+/cm^2 at an energy of 150 keV/atom.
Date: December 1982
Creator: Hamdi, Aboud Helal
Partner: UNT Libraries