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Two-Phase Spray Cooling with Water/2-Propanol Binary Mixtures for High Heat Flux Focal Source

Description: Two-phase spray cooling has been an emerging thermal management technique offering high heat transfer coefficients and critical heat flux levels, near-uniform surface temperatures, and efficient coolant usage that enables to design of compact and lightweight systems. Due to these capabilities, spray cooling is a promising approach for high heat flux applications in computing, power electronics, and optics. Two-phase spray cooling inherently depends on saturation temperature-pressure relationships of the working fluid to take advantage of high heat transfer rates associated with liquid-vapor phase change. When a certain application requires strict temperature and/or pressure conditions, thermo-physical properties of the working fluid play a critical role in attaining proper efficiency, reliability, or packaging structure. However, some of the commonly used single-component working fluids have relatively poor properties and heat transfer performance. For example, water is the best coolant in terms of properties, yet in certain applications where the system operates at low temperature ambient, it cannot be implemented due to freezing risk. The common solution for this problem is to use the antifreeze mixtures (binary mixtures of water and alcohol) to reduce the freezing point. In such cases, utilizing binary mixtures to tune working fluid properties becomes an alternative approach. This study has two main objectives; (1) to experimentally investigate the two-phase spray cooling performance of water/2-propanol binary mixture, and (2) to numerically investigate the performance of an advanced heat spreader featuring high and directional thermal conductivity materials for high heat flux focal sources. The first part of the study involves experimental characterization of heat transfer performance. Tests are conducted on a small-scale, closed loop spray cooling system featuring a pressure atomized spray nozzle. The test section, made of copper, measures 10 mm x 10 mm x 2 mm with a plain, smooth surface. A cylindrical copper block, with a matching size square ...
Date: December 2016
Creator: Obuladinne, Sai Sujith
Partner: UNT Libraries

Dynamic Behaviors of Historical Wrought Iron Truss Bridges – a Field Testing Case Study

Description: Civil infrastructure throughout the world serves as main arteries for commerce and transportation, commonly forming the backbone of many societies. Bridges have been and remain a crucial part of the success of these civil networks. However, the crucial elements have been built over centuries and have been subject to generations of use. Many current bridges have outlived their intended service life or have been retrofitted to carry additional loads over their original design. A large number of these historic bridges are still in everyday use and their condition needs to be monitored for public safety. Transportation infrastructure authorities have implemented various inspection and management programs throughout the world, mainly visual inspections. However, careful visual inspections can provide valuable information but it has limitations in that it provides no actual stress-strain information to determine structural soundness. Structural Health Monitoring (SHM) has been a growing area of research as officials need to asses and triage the aging infrastructure with methods that provide measurable response information to determine the health of the structure. A rapid improvement in technology has allowed researchers to start using new sensors and algorithms to understand the structural parameters of tested structures due to known and unknown loading scenarios. One of the most promising methods involves the use of wireless sensor nodes to measure structural responses to loads in real time. The structural responses can be processed to help understand the modal parameters, determine the health of the structure, and potentially identify damage. For example, modal parameters of structures are typically used when designing the lateral system of a structure. A better understanding of these parameters can lead to better and more efficient designs. Usually engineers rely on a finite element analysis to identify these parameters. By observing the actual parameters displayed during field testing, the theoretical FE models ...
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Date: December 2015
Creator: Hedric, Andrew C.
Partner: UNT Libraries

Comparative Analysis and Implementation of High Data Rate Wireless Sensor Network Simulation Frameworks

Description: This thesis focuses on developing a high data rate wireless sensor network framework that could be integrated with hardware prototypes to monitor structural health of buildings. In order to better understand the wireless sensor network architecture and its consideration in structural health monitoring, a detailed literature review on wireless sensor networks has been carried out. Through research, it was found that there are numerous simulation software packages available for wireless sensor network simulation. One suitable software was selected for modelling the framework. Research showed that Matlab/Simulink was the most suitable environment, and as a result, a wireless sensor network framework was designed in Matlab/Simulink. Further, the thesis illustrates modeling of a simple accelerometer sensor, such as those used in wireless sensor networks in Matlab/Simulink using a mathematical description. Finally, the framework operation is demonstrated with 10 nodes, and data integrity is analyzed with cyclic redundancy check and transmission error rate calculations.
Date: December 2015
Creator: Laguduva Rajaram, Madhupreetha
Partner: UNT Libraries

Exploring Process-Variation Tolerant Design of Nanoscale Sense Amplifier Circuits

Description: Sense amplifiers are important circuit components of a dynamic random access memory (DRAM), which forms the main memory of digital computers. The ability of the sense amplifier to detect and amplify voltage signals to correctly interpret data in DRAM cells cannot be understated. The sense amplifier plays a significant role in the overall speed of the DRAM. Sense amplifiers require matched transistors for optimal performance. Hence, the effects of mismatch through process variations must be minimized. This thesis presents a research which leads to optimal nanoscale CMOS sense amplifiers by incorporating the effects of process variation early in the design process. The effects of process variation on the performance of a standard voltage sense amplifier, which is used in conventional DRAMs, is studied. Parametric analysis is performed through circuit simulations to investigate which parameters have the most impact on the performance of the sense amplifier. The figures-of-merit (FoMs) used to characterize the circuit are the precharge time, power dissipation, sense delay and sense margin. Statistical analysis is also performed to study the impact of process variations on each FoM. By analyzing the results from the statistical study, a method is presented to select parameter values that minimize the effects of process variation. A design flow algorithm incorporating dual oxide and dual threshold voltage based techniques is used to optimize the FoMs for the sense amplifier. Experimental results prove that the proposed approach improves precharge time by 83.9%, sense delay by 80.2% sense margin by 61.9%, and power dissipation by 13.1%.
Date: December 2010
Creator: Okobiah, Oghenekarho
Partner: UNT Libraries

Comparison and Evaluation of Existing Analog Circuit Simulator using Sigma-Delta Modulator

Description: In the world of VLSI (very large scale integration) technology, there are many different types of circuit simulators that are used to design and predict the circuit behavior before actual fabrication of the circuit. In this thesis, I compared and evaluated existing circuit simulators by considering standard benchmark circuits. The circuit simulators which I evaluated and explored are Ngspice, Tclspice, Winspice (open source) and Spectre® (commercial). I also tested standard benchmarks using these circuit simulators and compared their outputs. The simulators are evaluated using design metrics in order to quantify their performance and identify efficient circuit simulators. In addition, I designed a sigma-delta modulator and its individual components using the analog behavioral language Verilog-A. Initially, I performed simulations of individual components of the sigma-delta modulator and later of the whole system. Finally, CMOS (complementary metal-oxide semiconductor) transistor-level circuits were designed for the differential amplifier, operational amplifier and comparator of the modulator.
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Date: December 2006
Creator: Ale, Anil Kumar
Partner: UNT Libraries

General Purpose Computing in Gpu - a Watermarking Case Study

Description: The purpose of this project is to explore the GPU for general purpose computing. The GPU is a massively parallel computing device that has a high-throughput, exhibits high arithmetic intensity, has a large market presence, and with the increasing computation power being added to it each year through innovations, the GPU is a perfect candidate to complement the CPU in performing computations. The GPU follows the single instruction multiple data (SIMD) model for applying operations on its data. This model allows the GPU to be very useful for assisting the CPU in performing computations on data that is highly parallel in nature. The compute unified device architecture (CUDA) is a parallel computing and programming platform for NVIDIA GPUs. The main focus of this project is to show the power, speed, and performance of a CUDA-enabled GPU for digital video watermark insertion in the H.264 video compression domain. Digital video watermarking in general is a highly computationally intensive process that is strongly dependent on the video compression format in place. The H.264/MPEG-4 AVC video compression format has high compression efficiency at the expense of having high computational complexity and leaving little room for an imperceptible watermark to be inserted. Employing a human visual model to limit distortion and degradation of visual quality introduced by the watermark is a good choice for designing a video watermarking algorithm though this does introduce more computational complexity to the algorithm. Research is being conducted into how the CPU-GPU execution of the digital watermark application can boost the speed of the applications several times compared to running the application on a standalone CPU using NVIDIA visual profiler to optimize the application.
Date: August 2014
Creator: Hanson, Anthony
Partner: UNT Libraries

Exploring Memristor Based Analog Design in Simscape

Description: With conventional CMOS technologies approaching their scaling limits, researchers are actively investigating alternative technologies for ever increasing computing and mobile demand. A number of different technologies are currently being studied by different research groups. In the last decade, one-dimensional (1D) carbon nanotubes (CNT), graphene, which is a two-dimensional (2D) natural occurring carbon rolled in tubular form, and zero-dimensional (0D) fullerenes have been the subject of intensive research. In 2008, HP Labs announced a ground-breaking fabrication of memristors, the fourth fundamental element postulated by Chua at the University of California, Berkeley in 1971. In the last few years, the memristor has gained a lot of attention from the research community. In-depth studies of the memristor and its analog behavior have convinced the community that it has the potential in future nano-architectures for optimization of high-density memory and neuromorphic computing architectures. The objective of this thesis is to explore memristors for analog and mixed-signal system design using Simscape. This thesis presents a memristor model in the Simscape language. Simscape has been used as it has the potential for modeling large systems. A memristor based programmable oscillator is also presented with simulation results and characterization. In addition, simulation results of different memristor models are presented which are crucial for the detailed understanding of the memristor along with its properties.
Date: May 2013
Creator: Gautam, Mahesh
Partner: UNT Libraries

Rapid Prototyping and Design of a Fast Random Number Generator

Description: Information in the form of online multimedia, bank accounts, or password usage for diverse applications needs some form of security. the core feature of many security systems is the generation of true random or pseudorandom numbers. Hence reliable generators of such numbers are indispensable. the fundamental hurdle is that digital computers cannot generate truly random numbers because the states and transitions of digital systems are well understood and predictable. Nothing in a digital computer happens truly randomly. Digital computers are sequential machines that perform a current state and move to the next state in a deterministic fashion. to generate any secure hash or encrypted word a random number is needed. But since computers are not random, random sequences are commonly used. Random sequences are algorithms that generate a pattern of values that appear to be random but after some time start repeating. This thesis implements a digital random number generator using MATLAB, FGPA prototyping, and custom silicon design. This random number generator is able to use a truly random CMOS source to generate the random number. Statistical benchmarks are used to test the results and to show that the design works. Thus the proposed random number generator will be useful for online encryption and security.
Date: May 2012
Creator: Franco, Juan
Partner: UNT Libraries

Rapid Prototyping and Design of a Fast Random Number Generator

Description: Information in the form of online multimedia, bank accounts, or password usage for diverse applications needs some form of security. the core feature of many security systems is the generation of true random or pseudorandom numbers. Hence reliable generators of such numbers are indispensable. the fundamental hurdle is that digital computers cannot generate truly random numbers because the states and transitions of digital systems are well understood and predictable. Nothing in a digital computer happens truly randomly. Digital computers are sequential machines that perform a current state and move to the next state in a deterministic fashion. to generate any secure hash or encrypted word a random number is needed. But since computers are not random, random sequences are commonly used. Random sequences are algorithms that generate a pattern of values that appear to be random but after some time start repeating. This thesis implements a digital random number generator using MATLAB, FGPA prototyping, and custom silicon design. This random number generator is able to use a truly random CMOS source to generate the random number. Statistical benchmarks are used to test the results and to show that the design works. Thus the proposed random number generator will be useful for online encryption and security.
Date: December 2011
Creator: Franco, Juan
Partner: UNT Libraries

Exploring Simscape™ Modeling for Piezoelectric Sensor Based Energy Harvester

Description: This work presents an investigation of a piezoelectric sensor based energy harvesting system, which collects energy from the surrounding environment. Increasing costs and scarcity of fossil fuels is a great concern today for supplying power to electronic devices. Furthermore, generating electricity by ordinary methods is a complicated process. Disposal of chemical batteries and cables is polluting the nature every day. Due to these reasons, research on energy harvesting from renewable resources has become mandatory in order to achieve improved methods and strategies of generating and storing electricity. Many low power devices being used in everyday life can be powered by harvesting energy from natural energy resources. Power overhead and power energy efficiency is of prime concern in electronic circuits. In this work, an energy harvester is modeled and simulated in Simscape™ for the functional analysis and comparison of achieved outcomes with previous work. Results demonstrate that the harvester produces power in the 0 μW to 100 μW range, which is an adequate amount to provide supply to low power devices. Power efficiency calculations also demonstrate that the implemented harvester is capable of generating and storing power for low power pervasive applications.
Date: May 2017
Creator: Dhayal, Vandana Sultan Singh
Partner: UNT Libraries

Effects of Minimum Quantity Lubrication in Drilling 1018 Steel.

Description: A common goal for industrial manufacturers is to create a safer working environment and reduce production costs. One common method to achieve this goal is to drastically reduce cutting fluid use in machining. Recent advances in machining technologies have made it possible to perform machining with minimum-quantity lubrication (MQL). Drilling takes a key position in the realization of MQL machining. In this study the effects of using MQL in drilling AISI 1018 steel with HSS tools using a vegetable based lubricant were investigated. A full factorial experiment was conducted and regression models were generated for both surface finish and hole size. Lower surface roughness and higher tool life were observed in the lowest speed and feed rate combination.
Date: December 2008
Creator: Shaikh, Vasim
Partner: UNT Libraries

Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System

Description: The design of VLSI electronic circuits can be achieved at many different abstraction levels starting from system behavior to the most detailed, physical layout level. As the number of transistors in VLSI circuits is increasing, the complexity of the design is also increasing, and it is now beyond human ability to manage. Hence CAD (Computer Aided design) or EDA (Electronic Design Automation) tools are involved in the design. EDA or CAD tools automate the design, verification and testing of these VLSI circuits. In today’s market, there are many EDA tools available. However, they are very expensive and require high-performance platforms. One of the key challenges today is to select appropriate CAD or EDA tools which are open-source for academic purposes. This thesis provides a detailed examination of an open-source EDA tool called Electric VLSI Design system. An excellent and efficient CAD tool useful for students and teachers to implement ideas by modifying the source code, Electric fulfills these requirements. This thesis' primary objective is to explain the Electric software features and architecture and to provide various digital and analog designs that are implemented by this software for educational purposes. Since the choice of an EDA tool is based on the efficiency and functions that it can provide, this thesis explains all the analysis and synthesis tools that electric provides and how efficient they are. Hence, this thesis is of benefit for students and teachers that choose Electric as their open-source EDA tool for educational purposes.
Date: May 2016
Creator: Aluru, Gunasekhar
Partner: UNT Libraries

Analysis and Optimization of Graphene FET based Nanoelectronic Integrated Circuits

Description: Like cell to the human body, transistors are the basic building blocks of any electronics circuits. Silicon has been the industries obvious choice for making transistors. Transistors with large size occupy large chip area, consume lots of power and the number of functionalities will be limited due to area constraints. Thus to make the devices smaller, smarter and faster, the transistors are aggressively scaled down in each generation. Moore's law states that the transistors count in any electronic circuits doubles every 18 months. Following this Moore's law, the transistor has already been scaled down to 14 nm. However there are limitations to how much further these transistors can be scaled down. Particularly below 10 nm, these silicon based transistors hit the fundamental limits like loss of gate control, high leakage and various other short channel effects. Thus it is not possible to favor the silicon transistors for future electronics applications. As a result, the research has shifted to new device concepts and device materials alternative to silicon. Carbon is the next abundant element found in the Earth and one of such carbon based nanomaterial is graphene. Graphene when extracted from Graphite, the same material used as the lid in pencil, have a tremendous potential to take future electronics devices to new heights in terms of size, cost and efficiency. Thus after its first experimental discovery of graphene in 2004, graphene has been the leading research area for both academics as well as industries. This dissertation is focused on the analysis and optimization of graphene based circuits for future electronics. The first part of this dissertation considers graphene based transistors for analog/radio frequency (RF) circuits. In this section, a dual gate Graphene Field Effect Transistor (GFET) is considered to build the case study circuits like voltage controlled oscillator (VCO) and low ...
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Date: May 2016
Creator: Joshi, Shital
Partner: UNT Libraries

Simulink(R) Based Design and Implementation of a Solar Power Based Mobile Charger

Description: Electrical energy is used at approximately the rate of 15 Terawatts world-wide. Generating this much energy has become a primary concern for all nations. There are many ways of generating energy among which the most commonly used are non-renewable and will extinct much sooner than expected. Very active research is going on both to increase the use of renewable energy sources and to use the available energy with more efficiency. Among these sources, solar energy is being considered as the most abundant and has received high attention. The mobile phone has become one of the basic needs of modern life, with almost every human being having one.Individually a mobile phone consumes little power but collectively this becomes very large. This consideration motivated the research undertaken in this masters thesis. The objective of this thesis is to design a model for solar power based charging circuits for mobile phone using Simulink(R). This thesis explains a design procedure of solar power based mobile charger circuit using Simulink(R) which includes the models for the photo-voltaic array, maximum power point tracker, pulse width modulator, DC-DC converter and a battery.The first part of the thesis concentrates on electron level behavior of a solar cell, its structure and its electrical model.The second part is to design an array of solar cells to generate the desired output.Finally, the third part is to design a DC-DC converter which can stabilize and provide the required input to the battery with the help of the maximum power point tracker and pulse width modulation.The obtained DC-DC converter is adjustable to meet the requirements of the battery. This design is aimed at charging a lithium ion battery with nominal voltage of 3.7 V, which can be taken as baseline to charge different types of batteries with different nominal voltages.
Date: May 2016
Creator: Mukka, Manoj Kumar
Partner: UNT Libraries

New Frameworks for Secure Image Communication in the Internet of Things (IoT)

Description: The continuous expansion of technology, broadband connectivity and the wide range of new devices in the IoT cause serious concerns regarding privacy and security. In addition, in the IoT a key challenge is the storage and management of massive data streams. For example, there is always the demand for acceptable size with the highest quality possible for images to meet the rapidly increasing number of multimedia applications. The effort in this dissertation contributes to the resolution of concerns related to the security and compression functions in image communications in the Internet of Thing (IoT), due to the fast of evolution of IoT. This dissertation proposes frameworks for a secure digital camera in the IoT. The objectives of this dissertation are twofold. On the one hand, the proposed framework architecture offers a double-layer of protection: encryption and watermarking that will address all issues related to security, privacy, and digital rights management (DRM) by applying a hardware architecture of the state-of-the-art image compression technique Better Portable Graphics (BPG), which achieves high compression ratio with small size. On the other hand, the proposed framework of SBPG is integrated with the Digital Camera. Thus, the proposed framework of SBPG integrated with SDC is suitable for high performance imaging in the IoT, such as Intelligent Traffic Surveillance (ITS) and Telemedicine. Due to power consumption, which has become a major concern in any portable application, a low-power design of SBPG is proposed to achieve an energy- efficient SBPG design. As the visual quality of the watermarked and compressed images improves with larger values of PSNR, the results show that the proposed SBPG substantially increases the quality of the watermarked compressed images. Higher value of PSNR also shows how robust the algorithm is to different types of attack. From the results obtained for the energy- efficient SBPG ...
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Date: August 2016
Creator: Albalawi, Umar Abdalah S
Partner: UNT Libraries

Hardware and Software Codesign of a JPEG2000 Watermarking Encoder

Description: Analog technology has been around for a long time. The use of analog technology is necessary since we live in an analog world. However, the transmission and storage of analog technology is more complicated and in many cases less efficient than digital technology. Digital technology, on the other hand, provides fast means to be transmitted and stored. Digital technology continues to grow and it is more widely used than ever before. However, with the advent of new technology that can reproduce digital documents or images with unprecedented accuracy, it poses a risk to the intellectual rights of many artists and also on personal security. One way to protect intellectual rights of digital works is by embedding watermarks in them. The watermarks can be visible or invisible depending on the application and the final objective of the intellectual work. This thesis deals with watermarking images in the discrete wavelet transform domain. The watermarking process was done using the JPEG2000 compression standard as a platform. The hardware implementation was achieved using the ALTERA DSP Builder and SIMULINK software to program the DE2 ALTERA FPGA board. The JPEG2000 color transform and the wavelet transformation blocks were implemented using the hardware-in-the-loop (HIL) configuration.
Date: December 2008
Creator: Mendoza, Jose Antonio
Partner: UNT Libraries

Simulink Based Modeling of a Multi Global Navigation Satellite System

Description: The objective of this thesis is to design a model for a multi global navigation satellite system using Simulink. It explains a design procedure which includes the models for transmitter and receiver for two different navigation systems. To overcome the problem, where less number of satellites are visible to determine location degrades the performance of any positioning system significantly, this research has done to make use of multi GNSS satellite signals in one navigation receiver.
Date: December 2016
Creator: Mukka, Nagaraju
Partner: UNT Libraries

A New N-way Reconfigurable Data Cache Architecture for Embedded Systems

Description: Performance and power consumption are most important issues while designing embedded systems. Several studies have shown that cache memory consumes about 50% of the total power in these systems. Thus, the architecture of the cache governs both performance and power usage of embedded systems. A new N-way reconfigurable data cache is proposed especially for embedded systems. This thesis explores the issues and design considerations involved in designing a reconfigurable cache. The proposed reconfigurable data cache architecture can be configured as direct-mapped, two-way, or four-way set associative using a mode selector. The module has been designed and simulated in Xilinx ISE 9.1i and ModelSim SE 6.3e using the Verilog hardware description language.
Date: December 2009
Creator: Bani, Ruchi Rastogi
Partner: UNT Libraries

CMOS Active Pixel Sensors for Digital Cameras: Current State-of-the-Art

Description: Image sensors play a vital role in many image sensing and capture applications. Among the various types of image sensors, complementary metal oxide semiconductor (CMOS) based active pixel sensors (APS), which are characterized by reduced pixel size, give fast readouts and reduced noise. APS are used in many applications such as mobile cameras, digital cameras, Webcams, and many consumer, commercial and scientific applications. With these developments and applications, CMOS APS designs are challenging the old and mature technology of charged couple device (CCD) sensors. With the continuous improvements of APS architecture, pixel designs, along with the development of nanometer CMOS fabrications technologies, APS are optimized for optical sensing. In addition, APS offers very low-power and low-voltage operations and is suitable for monolithic integration, thus allowing manufacturers to integrate more functionality on the array and building low-cost camera-on-a-chip. In this thesis, I explore the current state-of-the-art of CMOS APS by examining various types of APS. I show design and simulation results of one of the most commonly used APS in consumer applications, i.e. photodiode based APS. We also present an approach for technology scaling of the devices in photodiode APS to present CMOS technologies. Finally, I present the most modern CMOS APS technologies by reviewing different design models. The design of the photodiode APS is implemented using commercial CAD tools.
Date: May 2007
Creator: Palakodety, Atmaram
Partner: UNT Libraries

A nano-CMOS based universal voltage level converter for multi-VDD SoCs.

Description: Power dissipation of integrated circuits is the most demanding issue for very large scale integration (VLSI) design engineers, especially for portable and mobile applications. Use of multiple supply voltages systems, which employs level converter between two voltage islands is one of the most effective ways to reduce power consumption. In this thesis work, a unique level converter known as universal level converter (ULC), capable of four distinct level converting operations, is proposed. The schematic and layout of ULC are built and simulated using CADENCE. The ULC is characterized by performing three analysis such as parametric, power, and load analysis which prove that the design has an average power consumption reduction of about 85-97% and capable of producing stable output at low voltages like 0.45V even under varying load conditions.
Date: May 2007
Creator: Vadlmudi, Tripurasuparna
Partner: UNT Libraries

FPGA Prototyping of a Watermarking Algorithm for MPEG-4

Description: In the immediate future, multimedia product distribution through the Internet will become main stream. However, it can also have the side effect of unauthorized duplication and distribution of multimedia products. That effect could be a critical challenge to the legal ownership of copyright and intellectual property. Many schemes have been proposed to address these issues; one is digital watermarking which is appropriate for image and video copyright protection. Videos distributed via the Internet must be processed by compression for low bit rate, due to bandwidth limitations. The most widely adapted video compression standard is MPEG-4. Discrete cosine transform (DCT) domain watermarking is a secure algorithm which could survive video compression procedures and, most importantly, attacks attempting to remove the watermark, with a visibly degraded video quality result after the watermark attacks. For a commercial broadcasting video system, real-time response is always required. For this reason, an FPGA hardware implementation is studied in this work. This thesis deals with video compression, watermarking algorithms and their hardware implementation with FPGAs. A prototyping VLSI architecture will implement video compression and watermarking algorithms with the FPGA. The prototype is evaluated with video and watermarking quality metrics. Finally, it is seen that the video qualities of the watermarking at the uncompressed vs. the compressed domain are only 1dB of PSNR lower. However, the cost of compressed domain watermarking is the complexity of drift compensation for canceling the drifting effect.
Date: May 2007
Creator: Cai, Wei
Partner: UNT Libraries

VLSI Architecture and FPGA Prototyping of a Secure Digital Camera for Biometric Application

Description: This thesis presents a secure digital camera (SDC) that inserts biometric data into images found in forms of identification such as the newly proposed electronic passport. However, putting biometric data in passports makes the data vulnerable for theft, causing privacy related issues. An effective solution to combating unauthorized access such as skimming (obtaining data from the passport's owner who did not willingly submit the data) or eavesdropping (intercepting information as it moves from the chip to the reader) could be judicious use of watermarking and encryption at the source end of the biometric process in hardware like digital camera or scanners etc. To address such issues, a novel approach and its architecture in the framework of a digital camera, conceptualized as an SDC is presented. The SDC inserts biometric data into passport image with the aid of watermarking and encryption processes. The VLSI (very large scale integration) architecture of the functional units of the SDC such as watermarking and encryption unit is presented. The result of the hardware implementation of Rijndael advanced encryption standard (AES) and a discrete cosine transform (DCT) based visible and invisible watermarking algorithm is presented. The prototype chip can carry out simultaneous encryption and watermarking, which to our knowledge is the first of its kind. The encryption unit has a throughput of 500 Mbit/s and the visible and invisible watermarking unit has a max frequency of 96.31 MHz and 256 MHz respectively.
Date: August 2006
Creator: Adamo, Oluwayomi Bamidele
Partner: UNT Libraries

Design and Optimization of Components in a 45nm CMOS Phase Locked Loop

Description: A novel scheme of optimizing the individual components of a phase locked loop (PLL) which is used for stable clock generation and synchronization of signals is considered in this work. Verilog-A is used for the high level system design of the main components of the PLL, followed by the individual component wise optimization. The design of experiments (DOE) approach to optimize the analog, 45nm voltage controlled oscillator (VCO) is presented. Also a mixed signal analysis using the analog and digital Verilog behavior of components is studied. Overall a high level system design of a PLL, a systematic optimization of each of its components, and an analog and mixed signal behavioral design approach have been implemented using cadence custom IC design tools.
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Date: December 2006
Creator: Sarivisetti, Gayathri
Partner: UNT Libraries

A Verilog 8051 Soft Core for FPGA Applications

Description: The objective of this thesis was to develop an 8051 microcontroller soft core in the Verilog hardware description language (HDL). Each functional unit of the 8051 microcontroller was developed as a separate module, and tested for functionality using the open-source VHDL Dalton model as benchmark. These modules were then integrated to operate as concurrent processes in the 8051 soft core. The Verilog 8051 soft core was then synthesized in Quartus® II simulation and synthesis environment (Altera Corp., San Jose, CA, www.altera.com) and yielded the expected behavioral response to test programs written in 8051 assembler residing in the v8051 ROM. The design can operate at speeds up to 41 MHz and used only 16% of the FPGA fabric, thus allowing complex systems to be designed on a single chip. Further research and development can be performed on v8051 to enhance performance and functionality.
Date: August 2009
Creator: Rangoonwala, Sakina
Partner: UNT Libraries