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Transistorization of Nuclear Counting Circuits

Description: From Abstract: "The advantage of long operational life, low power drain and miniaturization may be realized in nuclear counting circuits through the use of transistors. The disadvantage of instability, due to the effects of temperature change in the transistor, may be minimized in counting circuit designs. Representative circuits of a binary stage, amplitude discriminator, one shot multivibrator, and ratemeters are included. These were designed using the criteria of an minimum Beta and a maximum Ico."
Date: August 19, 1957
Creator: Graveson, R. T. & Sadowski, H.
Partner: UNT Libraries Government Documents Department

The Influence of Ohmic Metals and Oxide Deposition on the Structure and Electrical Properties of Multilayer Epitaxial Graphene on Silicon Carbide Substrates

Description: Graphene has attracted significant research attention for next generation of semiconductor devices due to its high electron mobility and compatibility with planar semiconductor processing. In this dissertation, the influences of Ohmic metals and high dielectric (high-k) constant aluminum oxide (Al2O3) deposition on the structural and electrical properties of multi-layer epitaxial graphene (MLG) grown by graphitization of silicon carbide (SiC) substrates have been investigated. Uniform MLG was successfully grown by sublimation of silicon from epitaxy-ready, Si and C terminated, 6H-SiC wafers in high-vacuum and argon atmosphere. The graphene formation was accompanied by a significant enhancement of Ohmic behavior, and, was found to be sensitive to the temperature ramp-up rate and annealing time. High-resolution transmission electron microscopy (HRTEM) showed that the interface between the metal and SiC remained sharp and free of macroscopic defects even after 30 min, 1430 °C anneals. The impact of high dielectric constant Al2O3 and its deposition by radio frequency (RF) magnetron sputtering on the structural and electrical properties of MLG is discussed. HRTEM analysis confirms that the Al2O3/MLG interface is relatively sharp and that thickness approximation of the MLG using angle resolved X-ray photoelectron spectroscopy (ARXPS) as well as variable-angle spectroscopic ellipsometry (VASE) is accurate. The totality of results indicate that ARXPS can be used as a nondestructive tool to measure the thickness of MLG, and that RF sputtered Al2O3 can be used as a (high-k) constant gate oxide in multilayer grapheme based transistor applications.
Date: May 2011
Creator: Maneshian, Mohammad Hassan
Partner: UNT Libraries

Transistors: Counters

Description: Abstract: "Two transistor plug-in decade counters are described, one of which operates over the SCS-7 temperature range. A transistor digital scanner with storage and parallel readout is described. It utilizes one of the plug-in decades. A simple design procedure for flip-flops is presented."
Date: May 29, 1957
Creator: Pollard, Neith
Partner: UNT Libraries Government Documents Department

Designing a Micro-Mechanical Transistor

Description: This is the final report of a three-year, Laboratory-Directed Research and Development (LDRD) project at the Los Alamos National Laboratory (LANL). Micro-mechanical electronic systems are chips with moving parts. They are fabricated with the same techniques that are used to manufacture electronic chips, sharing their low cost. Micro-mechanical chips can also contain electronic components. By combining mechanical parts with electronic parts it becomes possible to process signal mechanically. To achieve designs comparable to those obtained with electronic components it is necessary to have a mechanical device that can change its behavior in response to a small input - a mechanical transistor. The work proposed will develop the design tools for these complex-shaped resonant structures using the geometrical ray technique. To overcome the limitations of geometrical ray chaos, the dynamics of the rays will be studied using the methods developed for the study of nonlinear dynamical systems. T his leads to numerical methods that execute well in parallel computer architectures, using a limited amount of memory and no inter-process communication.
Date: June 3, 1999
Creator: Mainieri, R.
Partner: UNT Libraries Government Documents Department

Electrical and Structure Properties of High-κ Barium Tantalite and Aluminum Oxide Interface with Zinc Oxide for Applications in Transparent Thin Film Transistors

Description: ZnO has generated interest for flexible electronics/optoelectronic applications including transparent thin film transistors (TFTs). For this application, low temperature processes that simultaneously yield good electrical conductivity and optical transparency and that are compatible with flexible substrates such as plastic, are of paramount significance. Further, gate oxides are a critical component of TFTs, and must exhibit low leakage currents and self-healing breakdown in order to ensure optimal TFTs switching performance and reliability. Thus, the objective of this work was twofold: (1) develop an understanding of the processing-structure-property relationships of ZnO and high-κ BaTa2O6 and Al2O3 (2) understand the electronic defect structure of BaTa2O6 /ZnO and Al2O3/ZnO interfaces and develop insight to how such interfaces may impact the switching characteristics (speed and switching power) of TFTs featuring these materials. Of the ZnO films grown by atomic layer deposition (ALD), pulsed laser deposition (PLD) and magnetron sputtering at 100-200 °C, the latter method exhibited the best combination of n-type electrical conductivity and optical transparency. These determinations were made using a combination of photoluminescence, photoluminescence excitation, absorption edge and Hall measurements. Metal-insulator-semiconductor devices were then fabricated with sputtered ZnO and high-κ BaTa2O6 and Al2O3 and the interfaces of high-κ BaTa2O6 and Al2O3 with ZnO were analyzed using frequency dependent C-V and G-V measurements. The insulator films were deposited at room temperature by magnetron sputtering using optimized processing conditions. Although the Al2O3 films exhibited a lower breakdown strength and catastrophic breakdown behavior compared to BaTa2O6/ZnO interface, the Al2O3/ZnO interface was characterized by more than an order of magnitude smaller density of interface traps and interface trapped charge. The BaTa2O6 films in addition were characterized by a significantly higher concentration of fixed oxide charge. The transition from accumulation to inversion in the Al2O3 MIS structure was considerably sharper, and occurred at less than one tenth of ...
Date: August 2011
Creator: Kuo, Fang-Ling
Partner: UNT Libraries

Transistor Driven Beam Switching Tube Decade Counter

Description: Abstract: "This paper describes an electrical readout, decade counter employing the magnetron beam switching tube with transistor drive. Double pulse resolution is one microsecond. The unit will accept a variety of transistor types and will tolerate supply voltage variations of +/- 20% at ambient temperatures up to 60 C. A "Pixie" neon indicator is driven without the use of additional transistors. A readout circuit for printer on punched paper tape is presented."
Date: August 11, 1959
Creator: Graham, Richard H.
Partner: UNT Libraries Government Documents Department

The Total Quality Approach to Transistor Testing and Device Allocation

Description: The purpose of this study is to design a transistor conversion system oriented toward quality categories rather than toward devices. Underlying this purpose are two working hypotheses: First, quality categories can be developed by capitalizing on transistor total quality and convertibility; second, a transistor conversion system oriented toward quality categories is superior to existing device-oriented methods.
Date: May 1971
Creator: Novak, Jarry Vaclav
Partner: UNT Libraries


Description: A bootstrapped-emitter-follower circuit that achieves an input impedance greater than 10/sup 7/ ohms with germanium transistors is described. The circuit is analyzed and compared with a single emitter follower and a super-alpha- connected emitter follower for input impedance characteristics. (auth)
Date: September 1, 1958
Creator: Baum, J.J.
Partner: UNT Libraries Government Documents Department


Description: A theoretical discussion is presented of the P-N junction theory and the junction transistor. A P-N juncion is where the two regions of a Ge crystal meet, one side of which is P-type, the other N-type. An NPN junction transistor consists of a single crystal, one end of which is N-type, a middle section which is P-type, and the composite end which is N-type. Silicon and Ge are the semiconductors commonly used. (W.L.H.)
Date: June 1, 1958
Creator: Leivo, W J
Partner: UNT Libraries Government Documents Department


Description: The solution time of analog multipliers using field-effect transistors is investigated. This time is ultimately limited by the charging time of the transistor junction. In typical devices suitable for analog multiplication, the charging time is found to be about 10 to 20 nsec for a multiplication error of < 1%. A four quadrant pulse amplitude multiplier circuit with a solution time equal to the transistor charging time is described. (auth)
Date: October 1, 1963
Creator: Radeka, V.
Partner: UNT Libraries Government Documents Department

GaN High Power Devices

Description: A brief review is given of recent progress in fabrication of high voltage GaN and AlGaN rectifiers, GaN/AlGaN heterojunction bipolar transistors, GaN heterostructure and metal-oxide semiconductor field effect transistors. Improvements in epitaxial layer quality and in fabrication techniques have led to significant advances in device performance.
Date: July 17, 2000
Creator: PEARTON,S.J.; REN,F.; ZHANG,A.P.; DANG,G.; CAO,X.A.; LEE,K.P. et al.
Partner: UNT Libraries Government Documents Department

Epitaxially-Grown GaN Junction Field Effect Transistors

Description: Junction field effect transistors (JFET) are fabricated on a GaN epitaxial structure grown by metal organic chemical vapor deposition (MOCVD). The DC and microwave characteristics of the device are presented. A junction breakdown voltage of 56 V is obtained corresponding to the theoretical limit of the breakdown field in GaN for the doping levels used. A maximum extrinsic transconductance (g<sub>m</sub>) of 48 mS/mm and a maximum source-drain current of 270 mA/mm are achieved on a 0.8 &micro; m gate JFET device at V<sub>GS</sub>= 1 V and V<sub>DS</sub>=15 V. The intrinsic transconductance, calculated from the measured g<sub>m</sub> and the source series resistance, is 81 mS/mm. The f<sub>T</sub> and f<sub>max</sub> for these devices are 6 GHz and 12 GHz, respectively. These JFETs exhibit a significant current reduction after a high drain bias is applied, which is attributed to a partially depleted channel caused by trapped hot-electrons in the semi-insulating GaN buffer layer. A theoretical model describing the current collapse is described, and an estimate for the length of the trapped electron region is given.
Date: May 19, 1999
Creator: Baca, A.G.; Chang, P.C.; Denbaars, S.P.; Lester, L.F.; Mishra, U.K.; Shul, R.J. et al.
Partner: UNT Libraries Government Documents Department

Fabrication and characterization of GaN junction field effect transistors

Description: Junction field effect transistors (JFET) were fabricated on a GaN epitaxial structure grown by metal organic chemical vapor deposition. The DC and microwave characteristics, as well as the high temperature performance of the devices were studied. These devices exhibited excellent pinch-off and a breakdown voltage that agreed with theoretical predictions. An extrinsic transconductance (g{sub m}) of 48 mS/mm was obtained with a maximum drain current (I{sub D}) of 270 mA/mm. The microwave measurement showed an f{sub T} of 6 GHz and an f{sub max} of 12 GHz. Both the I{sub D} and the g{sub m} were found to decrease with increasing temperature, possibly due to lower electron mobility at elevated temperatures. These JFETs exhibited a significant current reduction after a high drain bias was applied, which was attributed to a partially depleted channel caused by trapped electrons in the semi-insulating GaN buffer layer.
Date: January 11, 2000
Creator: Zhang, L.; Lester, L.F.; Baca, A.G.; Shul, R.J.; Chang, P.C.; Willison, C.L. et al.
Partner: UNT Libraries Government Documents Department


Description: Field effect transistors have been fabricated on high-purity germanium substrates using low-temperature technology. The aim of this work is to preserve the low density of trapping centers in high-quality starting material by low-temperature (&lt; 350 C) processing. The use of germanium promises to eliminate some of the traps which cause generation-recombination noise in silicon field-effect transistors (FET's) at low temperatures. Typically, the transconductance (g{sub m}) in the germanium FET's is 10 mA/V and the gate leakage can be less than 10{sup -12} A. Our present devices exhibit a large 1/f noise component and most of this noise must be eliminated if they are to be competitive with silicon FET's commonly used in high-resolution nuclear spectrometers.
Date: November 1, 1978
Creator: Hansen, William L.; Goulding, Frederick S. & Haller, Eugene E.
Partner: UNT Libraries Government Documents Department

Determination of late-time Gamma-Ray (60Co) sensitivity of single diffusion Lot 2N2222A transistors.

Description: Sandia National Laboratories (SNL) has embarked on a program to develop a methodology to use damage relations techniques (alternative experimental facilities, modeling, and simulation) to understand the time-dependent effects in transistors (and integrated circuits) caused by neutron irradiations in the Sandia Pulse Reactor-III (SPR-III) facility. The development of these damage equivalence techniques is necessary since SPR-III was shutdown in late 2006. As part of this effort, the late time {gamma}-ray sensitivity of a single diffusion lot of 2N2222A transistors has been characterized using one of the {sup 60}Co irradiation cells at the SNL Gamma Irradiation Facility (GIF). This report summarizes the results of the experiments performed at the GIF.
Date: August 1, 2008
Creator: DePriest, Kendall Russell; Kajder, Karen C. & Peters, Curtis D.
Partner: UNT Libraries Government Documents Department

A Planar Quantum Transistor Based on 2D-2D Tunneling in Double Quantum Well Heterostructures

Description: We report on our work on the double electron layer tunneling transistor (DELTT), based on the gate-control of two-dimensional -- two-dimensional (2D-2D) tunneling in a double quantum well heterostructure. While previous quantum transistors have typically required tiny laterally-defined features, by contrast the DELTT is entirely planar and can be reliably fabricated in large numbers. We use a novel epoxy-bond-and-stop-etch (EBASE) flip-chip process, whereby submicron gating on opposite sides of semiconductor epitaxial layers as thin as 0.24 microns can be achieved. Because both electron layers in the DELTT are 2D, the resonant tunneling features are unusually sharp, and can be easily modulated with one or more surface gates. We demonstrate DELTTs with peak-to-valley ratios in the source-drain I-V curve of order 20:1 below 1 K. Both the height and position of the resonant current peak can be controlled by gate voltage over a wide range. DELTTs with larger subband energy offsets ({approximately} 21 meV) exhibit characteristics that are nearly as good at 77 K, in good agreement with our theoretical calculations. Using these devices, we also demonstrate bistable memories operating at 77 K. Finally, we briefly discuss the prospects for room temperature operation, increases in gain, and high-speed.
Date: December 14, 1998
Creator: Baca, W.E.; Blount, M.A.; Hafich, M.J.; Lyo, S.K.; Moon, J.S.; Reno, J.L. et al.
Partner: UNT Libraries Government Documents Department

Double Barrier Resonant Tunneling Transistor with a Fully Two Dimensional Emitter

Description: A novel planar resonant tunneling transistor is demonstrated. The growth structure is similar to that of a double-barrier resonant tunneling diode (RTD), except for a fully two-dimensional (2D) emitter formed by a quantum well. Current is fed laterally into the emitter, and the 2D--2D resonant tunneling current is controlled by a surface gate. This unique device structure achieves figures-of-merit, i.e. peak current densities and peak voltages, approaching that of state-of-the-art RTDs. Most importantly, sensitive control of the peak current and voltage is achieved by gating of the emitter quantum well subband energy. This quantum tunneling transistor shows exceptional promise for ultra-high speed and multifunctional operation at room temperature.
Date: July 13, 2000
Partner: UNT Libraries Government Documents Department

GaN pnp bipolar junction transistors operated to 250 C

Description: The authors report on the dc performance of the first GaN pnp bipolar junction transistor. The structure was grown by MOCVD on c-plane sapphire substrates and mesas formed by low damage Inductively Coupled Plasma etching with a Cl{sub 2}/Ar chemistry. The dc characteristics were measured up to V{sub BC} of 65 V in common base mode and at temperatures up to 250 C. Under all conditions, I{sub C} {approximately} I{sub E}, indicating higher emitter injection efficiency. The offset voltage was {le} 2 V and devices were operated up to power densities of 40kW{center{underscore}dot}cm{sup {minus}2}.
Date: January 3, 2000
Creator: Zhang, A.P.; Dang, G.; Ren, F.; Han, J.; Monier, C.; Baca, A.G. et al.
Partner: UNT Libraries Government Documents Department

A Novel Non-Destructive Silicon-on-Insulator Nonvolatile Memory - LDRD 99-0750 Final Report

Description: Defects in silicon-on-insulator (SOI) buried oxides are normally considered deleterious to device operation. Similarly, exposing devices to hydrogen at elevated temperatures often can lead to radiation-induced charge buildup. However, in this work, we take advantage of as-processed defects in SOI buried oxides and moderate temperature hydrogen anneals to generate mobile protons in the buried oxide to form the basis of a ''protonic'' nonvolatile memory. Capacitors and fully-processed transistors were fabricated. SOI buried oxides are exposed to hydrogen at moderate temperatures using a variety of anneal conditions to optimize the density of mobile protons. A fast ramp cool down anneal was found to yield the maximum number of mobile protons. Unfortunately, we were unable to obtain uniform mobile proton concentrations across a wafer. Capacitors were irradiated to investigate the potential use of protonic memories for space and weapon applications. Irradiating under a negative top-gate bias or with no applied bias was observed to cause little degradation in the number of mobile protons. However, irradiating to a total dose of 100 krad(SiO{sub 2}) under a positive top-gate bias caused approximately a 100% reduction in the number of mobile protons. Cycling capacitors up to 10{sup 4} cycles had little effect on the switching characteristics. No change in the retention characteristics were observed for times up to 3 x 10{sup 4} s for capacitors stored unbiased at 200 C. These results show the proof-of-concept for a protonic nonvolatile memory. Two memory architectures are proposed for a protonic non-destructive, nonvolatile memory.
Date: November 1, 1999
Partner: UNT Libraries Government Documents Department

Advanced Technology for Source Drain Resistance Reduction in Nanoscale FinFETs

Description: Dual gate MOSFET structures such as FinFETs are widely regarded as the most promising option for continued scaling of silicon based transistors after 2010. This work examines key process modules that enable reduction of both device area and fin width beyond requirements for the 16nm node. Because aggressively scaled FinFET structures suffer significantly degraded device performance due to large source/drain series resistance (RS/D), several methods to mitigate RS/D such as maximizing contact area, silicide engineering, and epitaxially raised S/D have been evaluated.
Date: May 2008
Creator: Smith, Casey Eben
Partner: UNT Libraries