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Conductor Structures Including Penetrable Materials

Description: Patent relating to conductors used in electronic components and related fabrication methods, and more particularly to metal conductors for use in electronic components created by deposition of metals and related fabrication methods.
Date: February 24, 2004
Creator: Kelber, Jeffry A.; Lei, Jipu; Magtoto, Noel P. & Rudenja, Sergei
Partner: UNT College of Arts and Sciences

Performance of an MPI-only semiconductor device simulator on a quad socket/quad core InfiniBand platform.

Description: This preliminary study considers the scaling and performance of a finite element (FE) semiconductor device simulator on a capacity cluster with 272 compute nodes based on a homogeneous multicore node architecture utilizing 16 cores. The inter-node communication backbone for this Tri-Lab Linux Capacity Cluster (TLCC) machine is comprised of an InfiniBand interconnect. The nonuniform memory access (NUMA) nodes consist of 2.2 GHz quad socket/quad core AMD Opteron processors. The performance results for this study are obtained with a FE semiconductor device simulation code (Charon) that is based on a fully-coupled Newton-Krylov solver with domain decomposition and multilevel preconditioners. Scaling and multicore performance results are presented for large-scale problems of 100+ million unknowns on up to 4096 cores. A parallel scaling comparison is also presented with the Cray XT3/4 Red Storm capability platform. The results indicate that an MPI-only programming model for utilizing the multicore nodes is reasonably efficient on all 16 cores per compute node. However, the results also indicated that the multilevel preconditioner, which is critical for large-scale capability type simulations, scales better on the Red Storm machine than the TLCC machine.
Date: January 1, 2009
Creator: Shadid, John Nicolas & Lin, Paul Tinphone
Partner: UNT Libraries Government Documents Department

Micro-machined heat pipes in silicon MCM substrates

Description: Multichip modules (MCMs) containing power components need a substrate with excellent heat spreading capability both to avoid hot spots and to move dissipated heat toward the system heat sinks. Polycrystalline diamond is an excellent MCM heat spreading substrate but remains several orders of magnitude too expensive and somewhat more difficult to process than conventional mother-board materials. Today`s power MCMs concentrate on moderately priced silicon wafers and aluminum nitride ceramic with their improved thermal conductivity and good thermal expansion match to power semiconductor components, in comparison to traditional alumina and printed wiring board materials. However, even silicon and AlN substrates are challenged by designers` thermal needs. We report on the fabrication of micro-heat pipes embedded in silicon MCM substrates (5{times}5 cm) by the use of micromachined capillary wick structures and hermetic micro-cavities. This passive microstructure results in more than a 5 times improvement in heat spreading capability of the silicon MCM substrate over a large range of power densities and operating temperatures as compared with silicon alone. Thus diamond-like cooling is possible at silicon prices.
Date: December 31, 1995
Creator: Benson, D.A.; Mitchell, R.T.; Tuck, M.R.; Adkins, D.R. & Palmer, D.W.
Partner: UNT Libraries Government Documents Department

Simulation of plasma based semiconductor processing using block structured locally refined grids

Description: We have described a new numerical method for plasma simulation. Calculations have been presented which show that the method is accurate and suggest the regimes in which the method provides savings in CPU time and memory requirements. A steady state simulation of a four centimeter domain was modeled with sheath scale (150 microns) resolution using only 40 grid points. Simulations of semiconductor processing equipment have been performed which imply the usefulness of the method for engineering applications. It is the author`s opinion that these accomplishments represent a significant contribution to plasma simulation and the efficient numerical solution of certain systems of non-linear partial differential equations. More work needs to be done, however, for the algorithm to be of practical use in an engineering environment. Despite our success at avoiding the dielectric relaxation timestep restrictions the algorithm is still conditionally stable and requires timesteps which are relatively small. This represents a prohibitive runtime for steady state solutions on high resolution grids. Current research suggests that these limitations may be overcome and the use of much larger timesteps will be possible.
Date: January 1, 1998
Creator: Wake, D.D.
Partner: UNT Libraries Government Documents Department

Inductively Coupled Plasma and Electron Cyclotron Resonance Plasma Etching of InGaAlP Compound Semiconductor System

Description: Current and future generations of sophisticated compound semiconductor devices require the ability for submicron scale patterning. The situation is being complicated since some of the new devices are based on a wider diversity of materials to be etched. Conventional IUE (Reactive Ion Etching) has been prevalent across the industry so far, but has limitations for materials with high bond strengths or multiple elements. IrI this paper, we suggest high density plasmas such as ECR (Electron Cyclotron Resonance) and ICP (Inductively Coupled Plasma), for the etching of ternary compound semiconductors (InGaP, AIInP, AlGaP) which are employed for electronic devices like heterojunction bipolar transistors (HBTs) or high electron mobility transistors (HEMTs), and photonic devices such as light-emitting diodes (LEDs) and lasers. High density plasma sources, opeiating at lower pressure, are expected to meet target goals determined in terms of etch rate, surface morphology, surface stoichiometry, selectivity, etc. The etching mechanisms, which are described in this paper, can also be applied to other III-V (GaAs-based, InP-based) as well as III-Nitride since the InGaAIP system shares many of the same properties.
Date: November 4, 1998
Creator: Abernathy, C.R.; Hobson, W.S.; Hong, J.; Lambers, E.S.; Pearton, S.J. & Shul, R.J.
Partner: UNT Libraries Government Documents Department

Simulation of neutron radiation damage in silicon semiconductor devices.

Description: A code, Charon, is described which simulates the effects that neutron damage has on silicon semiconductor devices. The code uses a stabilized, finite-element discretization of the semiconductor drift-diffusion equations. The mathematical model used to simulate semiconductor devices in both normal and radiation environments will be described. Modeling of defect complexes is accomplished by adding an additional drift-diffusion equation for each of the defect species. Additionally, details are given describing how Charon can efficiently solve very large problems using modern parallel computers. Comparison between Charon and experiment will be given, as well as comparison with results from commercially-available TCAD codes.
Date: October 1, 2007
Creator: Shadid, John Nicolas; Hoekstra, Robert John; Hennigan, Gary Lee; Castro, Joseph Pete Jr. & Fixel, Deborah A.
Partner: UNT Libraries Government Documents Department

ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

Description: An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented.
Date: March 19, 2002
Creator: Anghinolfi, F.; Bialas, W.; Busek, N.; Ciocio, A.; Cosgrove, D.; Fadeyev, V. et al.
Partner: UNT Libraries Government Documents Department

Extremely high frequency RF effects on electronics.

Description: The objective of this work was to understand the fundamental physics of extremely high frequency RF effects on electronics. To accomplish this objective, we produced models, conducted simulations, and performed measurements to identify the mechanisms of effects as frequency increases into the millimeter-wave regime. Our purpose was to answer the questions, 'What are the tradeoffs between coupling, transmission losses, and device responses as frequency increases?', and, 'How high in frequency do effects on electronic systems continue to occur?' Using full wave electromagnetics codes and a transmission-line/circuit code, we investigated how extremely high-frequency RF propagates on wires and printed circuit board traces. We investigated both field-to-wire coupling and direct illumination of printed circuit boards to determine the significant mechanisms for inducing currents at device terminals. We measured coupling to wires and attenuation along wires for comparison to the simulations, looking at plane-wave coupling as it launches modes onto single and multiconductor structures. We simulated the response of discrete and integrated circuit semiconductor devices to those high-frequency currents and voltages, using SGFramework, the open-source General-purpose Semiconductor Simulator (gss), and Sandia's Charon semiconductor device physics codes. This report documents our findings.
Date: January 1, 2012
Creator: Loubriel, Guillermo Manuel; Vigliano, David; Coleman, Phillip Dale; Williams, Jeffery Thomas; Wouters, Gregg A.; Bacon, Larry Donald et al.
Partner: UNT Libraries Government Documents Department

Correlation method for the measure of mask-induced line-edge roughness in extreme ultraviolet lithography

Description: As critical dimensions for leading-edge semiconductor devices shrink, line-edge roughness (LER) requirements are pushing well into the single digit nanometer regime. At these scales many new sources of LER must be considered. In the case of extreme ultraviolet (EUV) lithography, modeling has shown the lithographic mask to be a source of significant concern. Here we present a correlation-based methodology for experimentally measuring the magnitude of mask contributors to printed LER. The method is applied to recent printing results from a 0.3 numerical aperture EUV microfield exposure tool. The measurements demonstrate that such effects are indeed present and of significant magnitude. The method is also used to explore the effects of illumination coherence and defocus and has been used to verify model-based predictions of mask-induced LER.
Date: May 25, 2009
Creator: Naulleau, Patrick
Partner: UNT Libraries Government Documents Department

Current trends in the packaging of photonic devices

Description: Optoelectronic and photonic devices hold great promise for high data-rate communication and computing. Their wide implementation was limited first by the device technologies and now suffers due to the need for high-precision packaging that is mass-produced. The use of photons as a medium of communication and control implies a unique set of packaging constraints that are highly driven by the need for micron and even sub-micron alignments between photonic devices and their transmission media. Current trends in optoelectronic device packaging are reviewed and future directions are identified both for free-space (3-dimensional) and guided-wave (2-dimensional) photonics. Emphasis will be placed on the special needs generated by increasing levels of device integration.
Date: April 1, 1995
Creator: Carson, R.F.
Partner: UNT Libraries Government Documents Department

Supercritical carbon dioxide extraction of solvent from micromachined structures

Description: We have demonstrated that supercritical carbon dioxide extraction can be used for solvent removal to successfully release compliant surface micromachined structures on silicon wafers developed at Sandia National Laboratories. Structures that have been successfully extracted and released include single gear microengines, bridge and cantilever beams, pressure transducers, and experimental comb drive actuators. Since the supercritical fluid has negligible surface tension, it has virtually unabated access to solvent residing in capillary-like spaces as narrow as 1--3 {mu}m under the micromachined features. While conventional drying techniques have been plagued with the collapse and sticking of micromachined structures due to surface tension effects, supercritical carbon dioxide has been shown to reproducibly dry components and test structures, including bridge and cantilever beams approaching 1000 {mu}m in length, without collapsing. The equipment and the extraction process are described, and photographs of supercritically dried test structures and components are presented.
Date: December 31, 1995
Creator: Russick, E.M.; Adkins, C.L.J. & Dyck, C.W.
Partner: UNT Libraries Government Documents Department

Metallization and packaging of compound semiconductor devices at Sandia National Laboratories

Description: Recent advances in compound semiconductor technology utilize a variety of metal thin films fabricated by thermal and electron-beam evaporation, and electroplating. An overview of metal processes used by Sandia`s Compound Semiconductor Research Laboratory is presented. Descriptions of electrical n-type and p-type ohmic contact alloys, interconnect metal, and metal layers specifically included for packaging requirements are addressed. Several illustrations of devices incorporating gold plated air bridges are included. ``Back-end`` processes such as flip-chip under bump metallurgy with fluxless solder reflow and plated solder processes are mentioned as current research areas.
Date: November 1, 1996
Creator: Seigal, P.K.; Armendariz, M.G.; Rieger, D.J.; Lear, K.L. & Sullivan, C.T.
Partner: UNT Libraries Government Documents Department

Theoretical tools for semiconductors devices

Description: This is the final report of a three-year, Laboratory-Directed Research and Development (LDRD) project at the Los Alamos National Laboratory (LANL). Future generations of Very Large Scale Integrated (VLSI) circuits require semiconducting devices that are much faster and smaller than current devices. Three-dimensional and transient effects are critical to the performance of these devices. Yet using Monte Carlo (MC) codes to perform time-dependent, three-dimensional simulations will not be feasible in the foreseeable future. Here we re-analyze the physics of semiconductors; use singular perturbation techniques to derive the reduced-dimensionality equations that accurately describe the semiconductor in the regimes corresponding to ultra-small ultra-fast devices; and validate the resulting theoretical models against MC simulations and experimental data. The objective of this project was to gain the capability of accurately simulating ultra-small ultra-fast devices in three spatial dimensions with the ultimate goal of transforming the design of advanced devices.
Date: October 1, 1996
Creator: Hagan, P.; Cox, R.; Randall, E. & Reyna, L.
Partner: UNT Libraries Government Documents Department

Sub-surface characterization and three dimensional profiling of semiconductors by magnetic resonance force microscopy

Description: This is the final report of a two-year, Laboratory-Directed Research and Development (LDRD) project at the Los Alamos National Laboratory (LANL). The project successfully developed a magnetic resonance force microscope (MRFM) instrument to mechanically detect magnetic resonance signals. This technique provides an intrinsically subsurface, chemical-species-specific probe of structure, constituent density and other properties of materials. As in conventional magnetic resonance imaging (MRI), an applied magnetic field gradient selects a well defined volume of the sample for study. However mechanical detection allows much greater sensitivity, and this in turn allows the reduction of the size of the minimum resolvable volume. This requires building an instrument designed to achieve nanometer-scale resolution at buried semiconductor interfaces. High-resolution, three-dimensional depth profiling of semiconductors is critical in the development and fabrication of semiconductor devices. Currently, there is no capability for direct, high-resolution observation and characterization of dopant density, and other critical features of semiconductors. The successful development of MRFM in conjunction with modifications to improve resolution will enable for the first time detailed structural and electronic studies in doped semiconductors and multilayered nanoelectronic devices, greatly accelerating the current pace of research and development.
Date: October 1, 1996
Creator: Hammel, P.C.; Moore, G.; Roukes, M. & Zhang, Zhenyong
Partner: UNT Libraries Government Documents Department

NIST energy related inventions - electronic starter device for fluorescent lamps. Final report

Description: Due to silicon supplier failures to produce the 03/04 triac silicon as specified in the original proposal, the direction of the starter program was migrated to use available off the shelf power semiconductors. This had unexpected positive side effects including a reduction in component price, improved quality, and the refocus of engineering efforts to concentrate on the Super ASIC core technology. The starter program has begun shipments employing this new architecture, and is being well received both in the US and abroad. In its present form, the starter meets the original cost projections within 20%. Work is continuing on the 0.8 micron ASIC, which will allow for the starter to sell below $1.00 in volume. Even at the slightly higher price, interest is strong in replacing the low performance glow starter for small fluorescent applications with a high performance alternative.
Date: June 1, 1998
Partner: UNT Libraries Government Documents Department

SCB thermite igniter studies

Description: The authors report on recent studies comparing the ignition threshold of temperature cycled, SCB thermite devices with units that were not submitted to temperature cycling. Aluminum/copper-oxide thermite was pressed into units at two densities, 45% of theoretical maximum density (TMD) or 47% of TMD. Half of each of the density sets underwent three thermal cycles; each cycle consisted of 2 hours at 74 C and 2 hours at {minus}54 C, with a 5 minute maximum transfer time between temperatures. The temperature cycled units were brought to ambient temperature before the threshold testing. Both the density and the thermal cycling affected the all-fire voltage. Using a 5.34 {micro}F CDU (capacitor discharge unit) firing set, the all-fire voltage for the units that were not temperature cycled increased with density from 32.99 V (45% TMD) to 39.32 V (47% TMD). The all-fire voltages for the thermally cycled units were 34.42 V (45% TMD) and 58.1 V (47% TMD). They also report on no-fire levels at ambient temperature for two component designs; the 5 minute no-fire levels were greater than 1.2 A. Units were also subjected to tests in which 1 W of RF power was injected into the bridges at 10 MHz for 5 minutes. The units survived and fired normally afterwards. Finally, units were subjected to pin-to-pin electrostatic discharge (ESD) tests. None of the units fired upon application of the ESD pulse, and all of the tested units fired normally afterwards.
Date: December 31, 1996
Creator: Bickes, R.W. Jr.; Wackerbarth, D.E. & Mohler, J.H.
Partner: UNT Libraries Government Documents Department

SETEC/Semiconductor Manufacturing Technologies Program: 1999 Annual and Final Report

Description: This report summarizes the results of work conducted by the Semiconductor Manufacturing Technologies Program at Sandia National Laboratories (Sandia) during 1999. This work was performed by one working group: the Semiconductor Equipment Technology Center (SETEC). The group's projects included Numerical/Experimental Characterization of the Growth of Single-Crystal Calcium Fluoride (CaF{sub 2}); The Use of High-Resolution Transmission Electron Microscopy (HRTEM) Imaging for Certifying Critical-Dimension Reference Materials Fabricated with Silicon Micromachining; Assembly Test Chip for Flip Chip on Board; Plasma Mechanism Validation: Modeling and Experimentation; and Model-Based Reduction of Contamination in Gate-Quality Nitride Reactor. During 1999, all projects focused on meeting customer needs in a timely manner and ensuring that projects were aligned with the goals of the National Technology Roadmap for Semiconductors sponsored by the Semiconductor Industry Association and with Sandia's defense mission. This report also provides a short history of the Sandia/SEMATECH relationship and a brief on all projects completed during the seven years of the program.
Date: December 2000
Creator: McBrayer, John D.
Partner: UNT Libraries Government Documents Department

Electrical breakdown in thin oxides during bias-temperature ramps

Description: Electrical breakdown in thin oxides is assessed by a new bias-temperature ramp technique. No significant effect of radiation exposure on breakdown is observed for high quality thermal and nitrided oxides, up to 20 Mrad(SiO{sub 2}).
Date: February 8, 2000
Partner: UNT Libraries Government Documents Department

Automated analysis of failure event data

Description: This paper focuses on fully automated analysis of failure event data in the concept and early development stage of a semiconductor-manufacturing tool. In addition to presenting a wide range of statistical and machine-specific performance information, algorithms have been developed to examine reliability growth and to identify major contributors to unreliability. These capabilities are being implemented in a new software package called Reliadigm. When coupled with additional input regarding repair times and parts availability, the analysis software also provides spare parts inventory optimization based on genetic optimization methods. The type of question to be answered is: If this tool were placed with a customer for beta testing, what would be the optimal spares kit to meet equipment reliability goals for the lowest cost? The new algorithms are implemented in Windows{reg_sign} software and are easy to apply. This paper presents a preliminary analysis of failure event data from three IDEA machines currently in development. The paper also includes an optimal spare parts kit analysis.
Date: March 27, 2000
Partner: UNT Libraries Government Documents Department