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Assessing the operational life of flexible printed boards intended for continuous flexing applications : a case study.

Description: Through the vehicle of a case study, this paper describes in detail how the guidance found in the suite of IPC (Association Connecting Electronics Industries) publications can be applied to develop a high level of design assurance that flexible printed boards intended for continuous flexing applications will satisfy specified lifetime requirements.
Date: January 1, 2011
Creator: Beck, David Franklin
Partner: UNT Libraries Government Documents Department

Capillary flow of solder on chemically roughened PWB surfaces

Description: The Center for Solder Science and Technology at Sandia National Laboratories has developed a solderability test for evaluating fundamental solder flow over PWB (printed wiring boards) surface finishes. The work supports a cooperative research and development agreement between Sandia, the National Center for Manufacturing Sciences (NCMS), and several industrial partners. An important facet of the effort involved the ``engineering`` of copper surfaces through mechanical and chemical roughening. The roughened topography enhances solder flow, especially over very fine features. In this paper, we describe how etching with different chemical solutions can affect solder flow on a specially designed ball grid array test vehicle (BGATV). The effects of circuit geometry, solution concentration, and etching time are discussed. Surface roughness and solder flow data are presented to support the roughening premise. Noticeable improvements in solder wettability were observed on uniformly etched surfaces having relatively steep peak-to-valley slopes.
Date: February 1, 1996
Creator: Hosking, F.M.; Stevenson, J.O. & Yost, F.G.
Partner: UNT Libraries Government Documents Department

A one piece wall box for space electronics

Description: In extraterrestrial applications, satellite payloads have printed circuit modules that are housed in boxes or chassis. The box may be a one piece wall or a segmented wall. These two wall options are compared for function and cost.
Date: May 1, 1995
Creator: Greenwood, W.H.
Partner: UNT Libraries Government Documents Department

Exploring the Feasibility of Fabricating Micron-Scale Components Using Microcontact Printing LDRD Final Report

Description: Many microfabrication techniques are being developed for applications in microelectronics, microsensors, and micro-optics. Since the advent of microcomponents, designers have been forced to modify their designs to include limitations of current technology, such as the inability to make three-dimensional structures and the need for piece-part assembly. Many groups have successfully transferred a wide variety of patterns to both two-dimensional and three-dimensional substrates using microcontact printing. Microcontact printing is a technique in which a self-assembled monolayer (SAM) is patterned onto a substrate by transfer printing. The patterned layer can act as an etch resist or a foundation upon which to build new types of microstructures. We created a gold pattern with features as small as 1.2 {micro}m using microcontact printing and subsequent processing. This approach looks promising for constructing single-level structures such as microelectrode arrays and sensors. It can be a viable technique for creating three-dimensional structures such as microcoils and microsprings if the right equipment is available to achieve proper alignment, and if a means is available to connect the final parts to other components in subsequent assembly operations. Microcontact printing provides a wide variety of new opportunities in the fabrication of microcomponents, and increases the options of designers.
Date: June 1, 2003
Partner: UNT Libraries Government Documents Department

Packaging strategies for printed circuit board components. Volume I, materials & thermal stresses.

Description: Decisions on material selections for electronics packaging can be quite complicated by the need to balance the criteria to withstand severe impacts yet survive deep thermal cycles intact. Many times, material choices are based on historical precedence perhaps ignorant of whether those initial choices were carefully investigated or whether the requirements on the new component match those of previous units. The goal of this program focuses on developing both increased intuition for generic packaging guidelines and computational methodologies for optimizing packaging in specific components. Initial efforts centered on characterization of classes of materials common to packaging strategies and computational analyses of stresses generated during thermal cycling to identify strengths and weaknesses of various material choices. Future studies will analyze the same example problems incorporating the effects of curing stresses as needed and analyzing dynamic loadings to compare trends with the quasi-static conclusions.
Date: September 1, 2011
Creator: Neilsen, Michael K. (Kansas City Plant, Kansas City, MO); Austin, Kevin N.; Adolf, Douglas Brian; Spangler, Scott W.; Neidigk, Matthew Aaron & Chambers, Robert S.
Partner: UNT Libraries Government Documents Department

Physiomics Array: A Platform for Genome Research and Cultivation of Difficult-to-Cultivate Microorganisms Final Technical Report

Description: A scalable array technology for parametric control of high-throughput cell cultivations is demonstrated. The technology makes use of commercial printed circuit board (PCB) technology, integrated circuit sensors, and an electrochemical gas generation system. We present results for an array of eight 250 μl microbioreactors. Each bioreactor contains an independently addressable suite that provides closed-loop temperature control, generates feed gas electrochemically, and continuously monitors optical density. The PCB technology allows for the assembly of additional off-the-shelf components into the microbioreactor array; we demonstrate the use of a commercial ISFET chip to continuously monitor culture pH. The electrochemical dosing system provides a powerful paradigm for reproducible gas delivery to high-density arrays of microreactors. We have scaled the technology to a standard 96-well format and have constructed a system that could be easily assembled.
Date: July 10, 2006
Creator: Keasling, Jay D.
Partner: UNT Libraries Government Documents Department

Thermophoresis and Its Thermal Parameters for Aerosol Collection

Description: The particle collection efficiency of a prototype environmental tobacco smoke (ETS) sampler based on the use of thermophoresis is determined by optimizing the operational voltage that determines its thermal gradient. This sampler's heating element was made of three sets of thermophoretic (TP) wires 25mu m in diameter suspended across a channel cut in a printed circuit board and mounted with collection surfaces on both sides. The separation between the heating element and the room temperature collection surface was determined in a numerical simulation based on the Brock-Talbot model. Other thermal parameters of this TP ETS sampler were predicted by the Brock-Talbot model for TP deposition. From the normalized results the optimal collection ratio was expressed in terms of operational voltage and fi lter mass. Prior to the Brock-Talbot model simulation for this sampler, 1.0V was used arbitrarily. The operational voltage was raised to 3.0V, and the collection effi ciency was increased by a factor of fi ve for both theory and experiment.
Date: August 1, 2007
Creator: Huang, Z.; Apte, Michael & Gundel, Lara
Partner: UNT Libraries Government Documents Department


Description: Several recent applications of superconducting magnets require the magnets to be operated at high ramp rates and at frequencies of several Hertz. Brookhaven National Laboratory (BNL) has recently designed and built prototypes of superconducting dipole magnets that can be ramped at a fairly high rate (1 T/s or more). For accelerator applications, it is also crucial that the magnets maintain good field quality even at high ramp rates. In order to characterize the field quality of magnets at high ramp rates, a measurement system consisting of 16 printed circuit tangential coils has been developed. The coil system is held stationary while the magnet is ramped. This paper describes the techniques used for the measurements and data analysis, and presents the results of measurements at ramp rates of up to 4 T/s in a prototype dipole built at BNL for GSI.
Date: September 18, 2006
Partner: UNT Libraries Government Documents Department

Extremely high frequency RF effects on electronics.

Description: The objective of this work was to understand the fundamental physics of extremely high frequency RF effects on electronics. To accomplish this objective, we produced models, conducted simulations, and performed measurements to identify the mechanisms of effects as frequency increases into the millimeter-wave regime. Our purpose was to answer the questions, 'What are the tradeoffs between coupling, transmission losses, and device responses as frequency increases?', and, 'How high in frequency do effects on electronic systems continue to occur?' Using full wave electromagnetics codes and a transmission-line/circuit code, we investigated how extremely high-frequency RF propagates on wires and printed circuit board traces. We investigated both field-to-wire coupling and direct illumination of printed circuit boards to determine the significant mechanisms for inducing currents at device terminals. We measured coupling to wires and attenuation along wires for comparison to the simulations, looking at plane-wave coupling as it launches modes onto single and multiconductor structures. We simulated the response of discrete and integrated circuit semiconductor devices to those high-frequency currents and voltages, using SGFramework, the open-source General-purpose Semiconductor Simulator (gss), and Sandia's Charon semiconductor device physics codes. This report documents our findings.
Date: January 1, 2012
Creator: Loubriel, Guillermo Manuel; Vigliano, David; Coleman, Phillip Dale; Williams, Jeffery Thomas; Wouters, Gregg A.; Bacon, Larry Donald et al.
Partner: UNT Libraries Government Documents Department

The Study and Implementation of Electrically Small Printed Antennas for an Integrated Transceiver Design

Description: This work focuses on the design and evaluation of the inverted-F, meandering-monopole, and loop antenna geometries. These printed antennas are studied with the goal of identifying which is suitable for use in a miniaturized transceiver design and which has the ability to provide superior performance using minimal Printed Circuit Board (PCB) space. As a result, the main objective is to characterize tradeoffs and identify which antenna provides the best compromise among volume, bandwidth and efficiency. For experimentation purposes, three types of meandering-monopole antenna are examined resulting in five total antennas for the study. The performance of each antenna under study is evaluated based upon return loss, operational bandwidth, and radiation pattern characteristics. For our purposes, return loss is measured using the S11-port reflection coefficient which helps to characterize how well the small antenna is able to be efficiently fed. Operational bandwidth is measured as the frequency range over which the antenna maintains 2:1 Voltage Standing Wave Ratio (VSWR) or equivalently has 10-dB return loss. Ansoft High Frequency Structure Simulator (HFSS) is used to simulate expected resonant frequency, bandwidth, VSWR, and radiation pattern characteristics. Ansoft HFSS simulation is used to provide a good starting point for antenna design before actual prototype are built using an LPKF automated router. Simulated results are compared with actual measurements to highlight any differences and help demonstrate the effects of antenna miniaturization. Radiation characteristics are measured illustrating how each antenna is affected by the influence of a non-ideal ground plane. The antenna with outstanding performance is further evaluated to determine its maximum range of communication. Each designs range performance is evaluated using a pair of transceivers to demonstrate round-trip communication. This research is intended to provide a knowledge base which will help decrease the number of design iterations needed for future implementation of products requiring integration ...
Date: April 15, 2009
Creator: Speer, Pete
Partner: UNT Libraries Government Documents Department

Document Template for Printed Circuit Board Layout

Description: The purpose of this document is to list the information that may be required to properly specify a printed circuit board (PCB) design. You must provide sufficient information to the PCB layout vendor such that they can quote accurately and design the PCB that you need. Use the following information as a guide to write your specification. Include as much of it as is necessary to get the PCB design that you want.
Date: January 1, 1998
Creator: Anderson, J. T.
Partner: UNT Libraries Government Documents Department

Description of a solder pulse generator for the single step formation of ball grid arrays

Description: The traditional geometry for surface mount devices is the peripheral array where the leads are on the edges of the device. As the technology drives towards high input/output (I/O) count (increasing number of leads) and smaller packages with finer pitch (less distance between peripheral leads), limitations on peripheral surface mount devices arise. The leads on these fine pitch devices are fragile and can be easily bent. It becomes increasingly difficult to deliver solder past to leads spaced as little as 0.012 inch apart. Too much solder mass can result in bridging between leads while too little solder can contribute to the loss of mechanical and electrical continuity. A solution is to shift the leads from the periphery of the device to the area under the device. This scheme is called areal array packaging and is exemplified by the ball grid array (BGA) package. A system has been designed and constructed to deposit an entire array of several hundred uniform solder droplets onto a printed circuit board in a fraction of a second. The solder droplets wet to the interconnect lands on a pc board and forms a basis for later application of a BGA device. The system consists of a piezoelectric solder pulse unit, heater controls, an inert gas chamber and an analog power supply/pulse unit.
Date: February 1, 1997
Creator: Schmale, D.T.; Frear, D.R.; Yost, F.G. & Essien, M.
Partner: UNT Libraries Government Documents Department

Mask substrate requirements and development for extreme ultraviolet lithography (EUVL)

Description: The mask is deemed one of the areas that require significant research and development in EUVL. Silicon wafers will be used for mask substrates for an alpha-class EUVL exposure tool due to their low-defect levels and high quality surface finish. However, silicon has a large coefficient of thermal expansion that leads to unacceptable image distortion due to absorption of EUV light. A low thermal expansion glass or glass-ceramic is likely to be required in order to meet error budgets for the 70nm node and beyond. Since EUVL masks are used in reflection, they are coated with multilayers prior to patterning. Surface imperfections, such as polishing marks, particles, scratches, or digs, are potential nucleation sites for defects in the multilayer coating, which could result in the printed defects. Therefore we are accelerating developments in the defect reduction and surface finishing of low thermal expansion mask substrates in order to understand long-term issues in controlling printable defects, and to establish the infrastructure for supplying masks. In this paper, we explain the technical requirements for EUVL mask substrates and describe our efforts in establishing a SEMI standard for EUVL masks. We will also report on the early progress of our suppliers in producing low thermal-expansion mask substrates for our development activities.
Date: September 28, 1999
Creator: Hector, S D; Shell, M; Taylor, J S & Tong, W M
Partner: UNT Libraries Government Documents Department

Appendix to the report from the low-residue soldering task force: Phase 2 results

Description: The LRSTF report for Phase I of its evaluation of low-residue soldering was issued in June 1995. This Appendix summarizes the results of follow-on testing performed in Phase II and compares electrical test results for both phases. Deliberate decisions were made by the LRSTF in Phase I to challenge the design guideline limits in MILSTD-275, Printed Wiring for Electronic Equipment The LRSTF considered this approach to produce a ``worst case`` design and provide useful information about the robustness of LR soldering processes. As such, good design practices were sometimes deliberately violated in designing the LRSTF board. This approach created some anomalies for both LR boards and RMA/cleaned controls. Phase II testing verified that problems that affected both RMA/cleaned and LR boards in Phase I were design related.
Date: December 1, 1995
Creator: Iman, R.L.; Anderson, D.J. & Huffman, D.D.
Partner: UNT Libraries Government Documents Department

Characterization of the embedded micromechanical device approach to the monolithic integration of MEMS with CMOS

Description: Recently, a great deal of interest has developed in manufacturing processes that allow the monolithic integration of MicroElectroMechanical Systems (MEMS) with driving, controlling, and signal processing electronics. This integration promises to improve the performance of micromechanical devices as well as lower the cost of manufacturing, packaging, and instrumenting these devices by combining the micromechanical devices with a electronic devices in the same manufacturing and packaging process. In order to maintain modularity and overcome some of the manufacturing challenges of the CMOS-first approach to integration, we have developed a MEMS-first process. This process places the micromechanical devices in a shallow trench, planarizes the wafer, and seals the micromechanical devices in the trench. Then, a high-temperature anneal is performed after the devices are embedded in the trench prior to microelectronics processing. This anneal stress-relieves the micromechanical polysilicon and ensures that the subsequent thermal processing associated with fabrication of the microelectronic processing does not adversely affect the mechanical properties of the polysilicon structures. These wafers with the completed, planarized micromechanical devices are then used as starting material for conventional CMOS processes. The circuit yield for the process has exceeded 98%. A description of the integration technology, the refinements to the technology, and wafer-scale parametric measurements of device characteristics is presented. Additionally, the performance of integrated sensing devices built using this technology is presented.
Date: October 1, 1996
Creator: Smith, J.H.; Montague, S.; Sniegowski, J.J. & Murray, J.R.
Partner: UNT Libraries Government Documents Department

Performance of a two-mirror, four-reflection, ring-field optical system at {lambda}=13 nm

Description: Performance of an Extreme Ultraviolet Lithography (EUVL) imaging optic was characterized by printing resolution test images in resist. While features as small as 0.137 {mu}m were successfully printed, a resolution of 0.175 {mu}m better represents the performance of the system over the full 0.9 mm{sup 2} image field. The contrast of the aerial image was estimated to be about 40% or less for the fine features printed. This low contrast value is attributed to a degradation of the modulation transfer function due to presence of scattered light in the image.
Date: May 24, 1996
Creator: La Fontaine, B.; Gaines, D.P.; Kania, D.R.; Sommargren, G.E.; Baker, S.L. & Ciarlo, D.
Partner: UNT Libraries Government Documents Department

Areal array jetting device for ball grid arrays

Description: Package designs for microelectronics devices have moved from through-hole to surface mount technology in order to increase the printed wiring board real estate available by utilizing both sides of the board. The traditional geometry for surface mount devices is peripheral arrays where the leads are on the edges of the device. As the technology drives towards high input/output (I/O) count (increasing number of leads) and smaller packages with finer pitch (less distance between peripheral leads), limitations on peripheral surface mount devices arise. A solution to the peripheral surface mount issue is to shift the leads to the area under the device. This scheme is called areal array packaging and is exemplified by the ball grid array (BGA) package. In a BGA package, the leads are on the bottom surface of the package in the form of an array of solder balls. The current practice of joining BGA packages to printed wiring boards involves a hierarchy of solder alloy compositions. A high melting temperature ball is typically used for standoff. A promising alternative to current methods is the use of jetting technology to perform monolithic solder ball attachment. This paper describes an areal array jetter that was designed and built to simultaneously jet arrays of solder balls directly onto BGA substrates.
Date: August 1, 1997
Creator: Frear, D.R.; Yost, F.G.; Schmale, D.T. & Essien, M.
Partner: UNT Libraries Government Documents Department