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GaAs Self-Aligned JFETS with Carbon-Doped P+ Region

Description: Self-aligned JFETs with a carbon-doped p{sup +} region have been reported for the first time. For these JFETs, both the channel and p{sup +} region were grown by metal organic chemical vapor deposition (MOCVD) and are termed epitaxial JFETs in this study. The epitaxial JFETs were compared to ion implanted JFETs of similar channel doping and threshold voltage. Both JFETs were fabricated using the same self-aligned process for doping the source and drain regions of the JFET and for eliminating excess gate capacitance of conventional JFETs. The gate turn-on voltage for the epitaxial JFETs was 1.06 V, about 0.1 V higher than for the implanted JFETs. The reverse breakdown voltage was similar for both JFETs but the reverse gate leakage current of the epitaxial JFETs was 1-3 orders of magnitude less than the implanted JFETs. The epitaxial JFETs also showed higher transconductance and lower knee voltage than the implanted JFETs.
Date: February 15, 1999
Creator: Allerman, A.A.; Baca, A.G.; Chang, P.C. & Drummond, T.J.
Partner: UNT Libraries Government Documents Department

A practical implementation of BICS for safety-critical applications

Description: This paper presents the challenges and solutions of applying Built-In-Current Sensors (BICS) to a safety-critical IC design for the purpose of in-situ state-of-health monitoring. The developed Quiscent Current Monitor (QCM) system consists of multiple BISC and digital control logic. The QCM BICS can detect leakage current as low as 4 {micro}A, run at system speed, and has relatively low real estate overhead. The QCM digital logic incorporates extensive debug capability and Built-In-Self-Test (BIST). The authors performed analog and digital simulations of the integrated BICS, and performed layout and tapeout of the design. Silicon is now in fabrication. Results to date show that, for some systems, BICS can be a practical and relatively inexpensive method for providing state-of-health monitoring of safety-critical microelectronics.
Date: February 9, 2000
Creator: SMITH,PATRICIA A. & CAMPBELL,DAVID V.
Partner: UNT Libraries Government Documents Department

Results from irradiation tests on D0 Run 2a silicon detectors at the Radiation Damage Facility at Fermilab

Description: Several different spare modules of the D0 experiment Silicon Microstrip Tracker (SMT) have been irradiated at the Fermilab Booster Radiation Damage Facility (RDF). The total dose received was 2.1 MRads with a proton flux of {approx} 3 {center_dot} 10{sup 11} p/cm{sup 2} sec. The irradiation was carried out in steps of 0.3 or 0.6 MRad, with several days between the steps to allow for annealing and measurements. The leakage currents and depletion voltages of the devices increased with dose, as expected from bulk radiation damage. The double sided, double metal devices showed worse degradation than the less complex detectors.
Date: March 1, 2006
Creator: Gardner, J.; Cerber, C.; Ke, Z.; Korjanevsky, S.; Leflat, A.; Lehner, F. et al.
Partner: UNT Libraries Government Documents Department

You Won`t Find These Leaks with a Blower Door: The Latest in "Leaking Electricity" in Homes

Description: Leaking electricity is the energy consumed by appliances when they are switched off or not performing their principal functions. Field measurements in Florida, California, and Japan show that leaking electricity represents 50 to 100 Watts in typical homes, corresponding to about 5 GW of total electricity demand in the United States. There are three strategies to reduce leaking electricity: eliminate leakage entirely, eliminate constant leakage and replace with intermittent charge plus storage, and improve efficiency of conversion. These options are constrained by the low value of energy savings-less than $5 per saved Watt. Some technical and lifestyle solutions are proposed. 13 refs., 1 fig., 2 tabs.
Date: August 1996
Creator: Rainer, L.; Greenberg, S. & Meier, A.
Partner: UNT Libraries Government Documents Department

High Voltage GaN Schottky Rectifiers

Description: Mesa and planar GaN Schottky diode rectifiers with reverse breakdown voltages (V{sub RB}) up to 550V and >2000V, respectively, have been fabricated. The on-state resistance, R{sub ON}, was 6m{Omega}{center_dot} cm{sup 2} and 0.8{Omega}cm{sup 2}, respectively, producing figure-of-merit values for (V{sub RB}){sup 2}/R{sub ON} in the range 5-48 MW{center_dot}cm{sup -2}. At low biases the reverse leakage current was proportional to the size of the rectifying contact perimeter, while at high biases the current was proportional to the area of this contact. These results suggest that at low reverse biases, the leakage is dominated by the surface component, while at higher biases the bulk component dominates. On-state voltages were 3.5V for the 550V diodes and {ge}15 for the 2kV diodes. Reverse recovery times were <0.2{micro}sec for devices switched from a forward current density of {approx}500A{center_dot}cm{sup -2} to a reverse bias of 100V.
Date: October 25, 1999
Creator: CAO,X.A.; CHO,H.; CHU,S.N.G.; CHUO,C.-C.; CHYI,J.-I.; DANG,G.T. et al.
Partner: UNT Libraries Government Documents Department

New Insights into Fully-Depleted SOI Transistor Response During Total-Dose Irradiation

Description: Previous work showed the possible existence of a total-dose latch effect in fully-depleted SOI transistors that could severely limit the radiation hardness of SOI devices. Other work showed that worst-case bias configuration during irradiation was the transmission gate bias configuration. In this work we further explore the effects of total-dose ionizing irradiation on fully-depleted SOI transistors. Closed-geometry and standard transistors fabricated in two fully-depleted processes were irradiated with 10-keV x rays. Our results show no evidence for a total-dose latch effect as proposed by others. Instead, in absence of parasitic trench sidewall leakage, our data suggests that the increase in radiation-induced leakage current is caused by positive charge trapping in the buried oxide inverting the back-channel interface. At moderate levels of trapped charge, the back-channel interface is slightly inverted causing a small leakage current to flow. This leakage current is amplified to considerably higher levels by impact ionization. Because the back-channel interface is in weak inversion, the top-gate bias can modulate the back-channel interface and turn the leakage current off at large, negative voltage levels. At high levels of trapped charge, the back-channel interface is fully inverted and the gate bias has little effect on leakage current. However, it is likely that this current also is amplified by impact ionization. For these transistors, the worst-case bias configuration was determined to be the ''ON'' bias configuration. These results have important implication on hardness assurance.
Date: September 14, 1999
Creator: BURNS,J.A.; DODD,PAUL E.; KEAST,C.L.; SCHWANK,JAMES R.; SHANEYFELT,MARTY R. & WYATT,P.W.
Partner: UNT Libraries Government Documents Department

Modeling and reduction of gate leakage during behavioral synthesis of nanoscale CMOS circuits.

Description: The major sources of power dissipation in a nanometer CMOS circuit are capacitive switching, short-circuit current, static leakage and gate oxide tunneling. However, with the aggressive scaling of technology the gate oxide direct tunneling current (gate leakage) is emerging as a prominent component of power dissipation. For sub-65 nm CMOS technology where the gate oxide (SiO2) thickness is very low, the direct tunneling current is the major form of tunneling. There are two contribution parts in this thesis: analytical modeling of behavioral level components for direct tunneling current and propagation delay, and the reduction of tunneling current during behavioral synthesis. Gate oxides of multiple thicknesses are useful in reducing the gate leakage dissipation. Analytical models from first principles to calculate the tunneling current and the propagation delay of behavioral level components is presented, which are backed by BSIM4/5 models and SPICE simulations. These components are characterized for 45 nm technology and an algorithm is provided for scheduling of datapath operations such that the overall tunneling current dissipation of a datapath circuit under design is minimal. It is observed that the oxide thickness that is being considered is very low it may not remain constant during the course of fabrication. Hence the algorithm takes process variation into consideration. Extensive experiments are conducted for various behavioral level benchmarks under various constraints and observed significant reductions, as high as 75.3% (with an average of 64.3%).
Access: This item is restricted to the UNT Community Members at a UNT Libraries Location.
Date: May 2006
Creator: Velagapudi, Ramakrishna
Partner: UNT Libraries

ADVANCED READOUT ELECTRONICS FOR MULTIELEMENT CdZnTe SENSORS.

Description: A generation of high performance front-end and read-out ASICs customized for highly segmented CdZnTe sensors is presented. The ASICs, developed in a multi-year effort at Brookhaven National Laboratory, are targeted to a wide range of applications including medical, safeguards/security, industrial, research, and spectroscopy. The front-end multichannel ASICs provide high accuracy low noise preamplification and filtering of signals, with versions for small and large area CdZnTe elements. They implement a high order unipolar or bipolar shaper, an innovative low noise continuous reset system with self-adapting capability to the wide range of detector leakage currents, a new system for stabilizing the output baseline and high output driving capability. The general-purpose versions include programmable gain and peaking time. The read-out multichannel ASICs provide fully data driven high accuracy amplitude and time measurements, multiplexing and time domain derandomization of the shaped pulses. They implement a fast arbitration scheme and an array of innovative two-phase offset-free rail-to-rail analog peak detectors for buffering and absorption of input rate fluctuations, thus greatly relaxing the rate requirement on the external ADC. Pulse amplitude, hit timing, pulse risetime, and channel address per processed pulse are available at the output in correspondence of an external readout request. Prototype chips have been fabricated in 0.5 and 0.35 {micro}m CMOS and tested. Design concepts and experimental results are discussed.
Date: July 8, 2002
Creator: DE GERONIMO,G.; O CONNOR,P.; KANDASAMY,A. & GROSHOLZ,J.
Partner: UNT Libraries Government Documents Department

An Automatic Lithium Drifting Apparatus for Silicon and Germanium Detectors

Description: Drifting a thick lithium-drifted counter (silicon and germanium) is a time-consuming operation that frequently results in a poor device, owing to inadequate knowledge of progress of the drifting operation. The drifting apparatus described here automatically controls the temperature of the detector that is being drifted to maintain the leakage current at a preselected value. While drifting proceeds, a continuous measurement is made of the distance of the lithium-drifted region from the opposite face of the wafer. When the drifted region reaches 30 mil or less from the back of the wafer a meter indicates the thickness of the undrifted region and, when this thickness falls below a preselected value, the temperature of the detector is automatically reduced to room temperature. The need for constant supervision of the drifting operation is thereby eliminated, and reliance on theoretical drift-rate calculations to predict the drift-through time is avoided. The technique has been applied to the manufacture of lithium-drifted silicon detectors with excellent results. The application of the technique to lithium-drifted germanium {gamma} detectors is also discussed briefly.
Date: February 8, 1964
Creator: Goulding, Fred S. & Hansen, W. L.
Partner: UNT Libraries Government Documents Department

Design, simulation, fabrication, and preliminary tests of 3D CMS pixel detectors for the super-LHC

Description: The Super-LHC upgrade puts strong demands on the radiation hardness of the innermost tracking detectors of the CMS, which cannot be fulfilled with any conventional planar detector design. The so-called 3D detector architectures, which feature columnar electrodes passing through the substrate thickness, are under investigation as a potential solution for the closest operation points to the beams, where the radiation fluence is estimated to reach 10{sup 16} n{sub eq}/cm{sup 2}. Two different 3D detector designs with CMS pixel readout electronics are being developed and evaluated for their advantages and drawbacks. The fabrication of full-3D active edge CMS pixel devices with p-type substrate has been successfully completed at SINTEF. In this paper, we study the expected post-irradiation behaviors of these devices with simulations and, after a brief description of their fabrication, we report the first leakage current measurement results as performed on wafer.
Date: January 1, 2010
Creator: Koybasi, Ozhan; U., /Purdue; Bortoletto, Daniela; U., /Purdue; Hansen, Thor-Erik; /SINTEF, Oslo et al.
Partner: UNT Libraries Government Documents Department

Irradiation study on GEM IPC preamp/shaper

Description: The Preamplifier/Shaper Integrated Circuit for the GEM Interpolating Pad Chamber (IPC), designed by Paul. O`Connor, Brookhaven National Laboratory is for amplifying the charge signal from the Pad cathodes into a voltage pulse which goes to the Analog Random Access Memory (ARAM) integrated circuit. The GEM IPC integrated circuit has a SemiGaussian voltage pulse output with a 30ns shaping time. The integrated circuits were fabricated using Harris Semiconductors AVLSI1-RA process in-order for the electronics on the wafer to survive up to 2 mad of ionizing radiation during its operation life time. The details of the electronics on the GEM IPC integrated circuits is explained in the design memorandum by Paul. O`Connor. The purpose of this study is to determine the ability of the electronics on this IC fabricated using the above process to withstand ionizing radiation up to the above mentioned dose level.
Date: January 1, 1995
Creator: Kandasamy, A.
Partner: UNT Libraries Government Documents Department

High resolution I{sub DDQ} characterization and testing -- Practical issues

Description: I{sub DDQ} testing has become an important contributor to quality improvement of CMOS ICs. This paper describes high resolution I{sub DDQ} characterization and testing (from the sub-nA to {micro}A level) and outlines test hardware and software issues. The physical basis of I{sub DDQ} is discussed. Methods for statistical analysis of I{sub DDQ} data are examined, as interpretation of the data is often as important as the measurement itself. Applications of these methods to set reasonable test limits for detecting defective product are demonstrated.
Date: December 1, 1996
Creator: Righter, A.W.; Soden, J.M. & Beegle, R.W.
Partner: UNT Libraries Government Documents Department

Interfacial arsenic from wet oxidation of Al{sub x}Ga{sub 1-X}As/GaAs: Its effects on electronic properties and new approaches to MIS device fabrication

Description: Three important oxidation regimes have been identified in the temporal evolution of the wet thermal oxidation of Al{sub x}Ga{sub 1-x}As (1 {ge} x {ge} 0.90) on GaAs: (1) oxidation of Al and Ga in the Al{sub x}Ga{sub 1-x}As alloy to form an amorphous oxide layer, (2) oxidative formation and elimination of elemental As (both crystalline and amorphous) and of amorphous As{sub 2}O{sub 3}, and (3) crystallization of the oxide film. Residual As can result in up to a 100-fold increase in leakage current and a 30% increase in the dielectric constant and produce strong Fermi-level pinning and high leakage currents at the oxidized Al{sub x}Ga{sub 1-x}As/GaAs interface. The presence of thermodynamically-favored interfacial As may impose a fundamental limitation on the application of AlGaAs wet oxidation for achieving MIS devices in the GaAs material system.
Date: December 31, 1996
Creator: Ashby, C.I.H.; Sullivan, J.P. & Newcomer, P.P.
Partner: UNT Libraries Government Documents Department

Alternative Gate Dielectrics on Semiconductors for MOSFET Device Applications

Description: We have investigated the synthesis and properties of deposited oxides on Si and Ge for use as alternative gate dielectrics in MOSFET applications. The capacitance and leakage current behavior of polycrystalline Y{sub 2}O{sub 3} films synthesized by pulsed-laser deposition is reported. In addition, we also discuss the growth of epitaxial oxide structures. In particular, we have investigated the use of silicide termination for oxide growth on (001) Si using laser-molecular beam epitaxy. In addition, we discuss a novel approach involving the use of hydrogen to eliminate native oxide during initial dielectric oxide nucleation on (001) Ge.
Date: December 6, 1999
Creator: Norton, D.P.; Budai, J.D.; Chisholm, M.F.; Pennycook, S.J.; McKee, R.; Walker, F. et al.
Partner: UNT Libraries Government Documents Department

Investigation of Ground-Fault Protection Devices for Photovoltaic Power Systems Applications

Description: Photovoltaic (PV) power systems, like other electrical systems, may be subject to unexpected ground faults. Installed PV systems always have invisible elements other than those indicated by their electrical schematics. Stray inductance, capacitance and resistance are distributed throughout the system. Leakage currents associated with the PV modules, the interconnected array, wires, surge protection devices and conduit add up and can become large enough to look like a ground-fault. PV systems are frequently connected to other sources of power or energy storage such as batteries, standby generators, and the utility grid. This complex arrangement of distributed power and energy sources, distributed impedance and proximity to other sources of power requires sensing of ground faults and proper reaction by the ground-fault protection devices. The different dc grounding requirements (country to country) often add more confusion to the situation. This paper discusses the ground-fault issues associated with both the dc and ac side of PV systems and presents test results and operational impacts of backfeeding commercially available ac ground-fault protection devices under various modes of operation. Further, the measured effects of backfeeding the tripped ground-fault devices for periods of time comparable to anti-islanding allowances for utility interconnection of PV inverters in the United States are reported.
Date: October 3, 2000
Creator: BOWER,WARD I. & WILES,JOHN
Partner: UNT Libraries Government Documents Department

Performance of CdZnTe detectors passivated with energetic oxygen atoms

Description: Noise caused by surface-leakage current can degrade the performance of CdZnTe spectrometers, particularly devices with closely spaced contacts such as coplanar grid detectors. In order to reduce surface leakage, the authors are treating CdZnTe detector surfaces with energetic, neutral oxygen atoms. Energetic oxygen atoms react with the surface to form a resistive oxide layer. Because the reaction is effective at room temperature, deleterious heating of the substrate is avoided. In most cases, leakage current and noise are shown to decrease significantly after treatment. The effect of the treatment on the performance of coplanar grid detectors is presented.
Date: December 1, 1998
Creator: Prettyman, T.H.; Hoffbauer, M.A. & Rennie, J.
Partner: UNT Libraries Government Documents Department

Studies of double-sided silicon microstrip detectors

Description: The electrical characteristics of detectors manufactured by SINTEF/SI with a variety of geometrical and processing options have been investigated. The detectors` leakage current, depletion voltage, bias resistance, interstrip resistance, coupling capacitance, and coupling capacitor breakdown voltage were studied.
Date: March 1, 1996
Creator: Seidel, S.C.; Bruner, N.L.; Frautsch, M.A.; Hoeferkamp, M.R. & Patton, A.
Partner: UNT Libraries Government Documents Department

Inductively Coupled Plasma-Induced Etch Damage of GaN p-n Junctions

Description: Plasma-induced etch damage can degrade the electrical and optical performance of III-V nitride electronic and photonic devices. We have investigated the etch-induced damage of an Inductively Coupled Plasma (ICP) etch system on the electrical performance of mesa-isolated GaN pn-junction diodes. GaN p-i-n mesa diodes were formed by Cl{sub 2}/BCl{sub 3}/Ar ICP etching under different plasma conditions. The reverse leakage current in the mesa diodes showed a strong relationship to chamber pressure, ion energy, and plasma flux. Plasma induced damage was minimized at moderate flux conditions ({le} 500 W), pressures {ge}2 mTorr, and at ion energies below approximately -275 V.
Date: November 3, 1999
Creator: SHUL,RANDY J.; ZHANG,LEI; BACA,ALBERT G.; WILLISON,CHRISTI LEE; HAN,JUNG; PEARTON,S.J. et al.
Partner: UNT Libraries Government Documents Department

The Radiation environment and damage in the CDF tracking volume

Description: The authors present direct measurements of the spatial distribution of ionizing radiation and low energy neutrons (E{sub n} < 200 keV) inside the tracking volume of the collider detector at Fermilab (CDF). Using data from multiple exposures, the radiation field can be separated into components from beam losses and collisions and can be checked for consistency between the measurements. They compare the radiation measurements with an increase in the leakage currents of the CDF silicon detectors and find reasonable agreement.
Date: December 16, 2003
Creator: al., R. J. Tesarek et
Partner: UNT Libraries Government Documents Department

Compact Gamma-Ray Imager for In-Vivo Gene Imaging

Description: A compact, low-cost, gamma-ray imaging system is needed to study gene expression in small animals. State-of-the-art electronic imaging systems have insufficient resolution and animals must be sacrificed for detailed imaging that precludes time evolution studies. With improved electronics radioactive tracers attached to gene markers can be used to track the absorption and mobility of gene therapy medications in live animals. Other instrumentation being developed for medical applications does not have the response to match the radiation source for this work. The objective of this research was to develop thick film (Cd,Zn)Te detectors matched to the gamma ray energy of {sup 129}I. The detector would be a direct readout device using p-i-n diodes formed from the high Z material absorbing the radiation, with separate readout. Higher quality semiconducting material was expected from epitaxial growth on GaAs, a near lattice matched substrate. In practice, it was difficult to obtain material with high resistance and low leakage current. Spire Corporation achieved the goal of fabricating working detectors in (Cd,Zn)Te deposited on GaAs. The spectra of an alpha emitter ({sup 225}Am) was adequately resolved in thin film devices. Thick p-i-n diodes were fabricated but other processing problems prevented full demonstration of a gamma ray detector.
Date: June 1, 2000
Creator: Greenwald, A. C.
Partner: UNT Libraries Government Documents Department

Diborane Electrode Response in 3D Silicon Sensors for the CMS and ATLAS Experiments

Description: Unusually high leakage currents have been measured in test wafers produced by the manufacturer SINTEF containing 3D pixel silicon sensor chips designed for the ATLAS (A Toroidal LHC ApparatuS) and CMS (Compact Muon Solenoid) experiments. Previous data has shown the CMS chips as having a lower leakage current after processing than ATLAS chips. Some theories behind the cause of the leakage currents include the dicing process and the usage of copper in bump bonding, and with differences in packaging and handling between the ATLAS and CMS chips causing the disparity between the two. Data taken at SLAC from a SINTEF wafer with electrodes doped with diborane and filled with polysilicon, before dicing, and with indium bumps added contradicts this past data, as ATLAS chips showed a lower leakage current than CMS chips. It also argues against copper in bump bonding and the dicing process as main causes of leakage current as neither were involved on this wafer. However, they still display an extremely high leakage current, with the source mostly unknown. The SINTEF wafer shows completely different behavior than the others, as the FEI3s actually performed better than the CMS chips. Therefore this data argues against the differences in packaging and handling or the intrinsic geometry of the two as a cause in the disparity between the leakage currents of the chips. Even though the leakage current in the FEI3s overall is lower, the current is still significant enough to cause problems. As this wafer was not diced, nor had it any copper added for bump bonding, this data argues against the dicing and bump bonding as causes for leakage current. To compliment this information, more data will be taken on the efficiency of the individual electrodes of the ATLAS and CMS chips on this wafer. The electrodes will be ...
Date: June 22, 2011
Creator: Brown, Emily R. & /SLAC, /Reed Coll.
Partner: UNT Libraries Government Documents Department

Babar Silicon Vertex Tracker: Status and Prospects

Description: The BABAR Silicon Vertex Tracker (SVT) has been efficiently operated for six years since the start of data taking in 1999. Due to higher than expected background levels some unforeseen effects have appeared. We discuss: a shift in the pedestal for the channels of the AToM readout chips that are most exposed to radiation; an anomalous increase in the bias leakage current for the modules in the outer layers. Estimates of future radiation doses and occupancies are shown together with the extrapolated detector performance and lifetime, in light of the new observations.
Date: April 27, 2006
Creator: Re, V.; Bondioli, M.; Bruinsma, M.; Curry, S.; Kirkby, D.; Berryhill, J. et al.
Partner: UNT Libraries Government Documents Department

Unlikely Combination of Experiments with a Novel High-Voltage CIGS Photovoltaic Array (Presentation)

Description: The goals of this study are to: (1) parameterize current-voltage (I-V) performance over a wide range of illumination and temperatures: (a) 50-1150 W/m{sup 2} irradiance, 5-65 C; (b) obtain array temperature coefficients; and (c) quantify energy production; (2) investigate high-voltage leakage currents from the CIS modules in a high-voltage array: determine dependence on moisture, temperature, and voltage bias and ascertain corrosion problems if any; and (3) study long-term power and energy production stability.
Date: May 1, 2006
Creator: del Cueto, J. A. & Sekulic, B. R.
Partner: UNT Libraries Government Documents Department

Surface current reduction of (211) oriented Cd0.46Zn0.04Te0.50 crystals by Ar bombardment

Description: Cd{sub 0.46}Zn{sub 0.04}Te{sub .50} crystals have been exposed to high density Ar plasmas in order to modify the surface chemistry and control the surface conductivity. X-ray photoelectron spectroscopy (XPS) reveals that this bombardment results in a modified surface atomic ratio, with Cd being preferentially removed compared to Te. In addition, the native oxide is removed and suppressed for an extended period of time. Current-voltage data is analyzed in order to determine the effect on surface leakage current after exposure. It is found that surface leakage current can be decreased by approximately 2.5 orders of magnitude following Ar{sup +} bombardment.
Date: March 16, 2010
Creator: Voss, L F; Beck, P R; Conway, A M; Graff, R T; Nikolic, R J; Nelson, A J et al.
Partner: UNT Libraries Government Documents Department