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open access

Delay locked loop integrated circuit.

Description: This report gives a description of the development of a Delay Locked Loop (DLL) integrated circuit (IC). The DLL was developed and tested as a stand-alone IC test chip to be integrated into a larger application specific integrated circuit (ASIC), the Quadrature Digital Waveform Synthesizer (QDWS). The purpose of the DLL is to provide a digitally programmable delay to enable synchronization between an internal system clock and external peripherals with unknown clock skew. The DLL was designed an… more
Date: October 1, 2007
Creator: Brocato, Robert Wesley
Partner: UNT Libraries Government Documents Department
open access

Charge Collection Studies on Integrated Circuit Test Structures using Heavy-Ion Microbeams and MEDICI Simulation Calculations

Description: Ion induced charge collection dynamics within Integrated Circuits (ICs) is important due to the presence of ionizing radiation in the IC environment. As the charge signals defining data states are reduced by voltage and area scaling, the semiconductor device will naturally have a higher susceptibility to ionizing radiation induced effects. The ionizing radiation can lead to the undesired generation and migration of charge within an IC. This can alter, for example, the memory state of a bit, and… more
Date: May 2000
Creator: Guo, Baonian
Partner: UNT Libraries
open access

A Materials Approach to Silicon Wafer Level Contamination Issues from the Wet Clean Process

Description: Semiconductor devices are built using hyperpure silicon and very controlled levels of doping to create desired electrical properties. Contamination can alter these precisely controlled electrical properties that can render the device non-functional or unreliable. It is desirable to determine what impurities impact the device and control them. This study consists of four parts: a) determination of acceptable SCI (Standard Clean 1) bath contamination levels using VPD-DSE-GFAAS (Vapor Phase Decomp… more
Date: December 1996
Creator: Hall, Lindsey H. (Lindsey Harrison)
Partner: UNT Libraries
open access

An Efficient Hybrid Heuristic and Probabilistic Model for the Gate Matrix Layout Problem in VLSI Design

Description: In this thesis, the gate matrix layout problem in VLSI design is considered where the goal is to minimize the number of tracks required to layout a given circuit and a taxonomy of approaches to its solution is presented. An efficient hybrid heuristic is also proposed for this combinatorial optimization problem, which is based on the combination of probabilistic hill-climbing technique and greedy method. This heuristic is tested experimentally with respect to four existing algorithms. As test ca… more
Date: August 1993
Creator: Bagchi, Tanuj
Partner: UNT Libraries
open access

Front-end electronics and trigger systems - status and challenges

Description: The past quarter century has brought about a revolution in front-end electronics for large-scale detector systems. Custom integrated circuits specifically tailored to the requirements of large detector systems have provided unprecedented performance and enabled systems that once were deemed impossible. The evolution of integrated circuit readouts in strip detectors is summarized, the present status described, and challenges posed by the sLHC and ILC are discussed. Performance requirements incre… more
Date: August 21, 2007
Creator: Spieler, Helmuth G & Spieler, Helmuth G
Partner: UNT Libraries Government Documents Department
open access

An Algorithm for the PLA Equivalence Problem

Description: The Programmable Logic Array (PLA) has been widely used in the design of VLSI circuits and systems because of its regularity, flexibility, and simplicity. The equivalence problem is typically to verify that the final description of a circuit is functionally equivalent to its initial description. Verifying the functional equivalence of two descriptions is equivalent to proving their logical equivalence. This problem of pure logic is essential to circuit design. The most widely used technique to … more
Date: December 1995
Creator: Moon, Gyo Sik
Partner: UNT Libraries

Comparison and Evaluation of Existing Analog Circuit Simulator using Sigma-Delta Modulator

Description: In the world of VLSI (very large scale integration) technology, there are many different types of circuit simulators that are used to design and predict the circuit behavior before actual fabrication of the circuit. In this thesis, I compared and evaluated existing circuit simulators by considering standard benchmark circuits. The circuit simulators which I evaluated and explored are Ngspice, Tclspice, Winspice (open source) and Spectre® (commercial). I also tested standard benchmarks using the… more
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Date: December 2006
Creator: Ale, Anil Kumar
Partner: UNT Libraries
open access

An Interactive Framework for Teaching Fundamentals of Digital Logic Design and VLSI Design

Description: Integrated Circuits (ICs) have a broad range of applications in healthcare, military, consumer electronics etc. The acronym VLSI stands for Very Large Scale Integration and is a process of making ICs by placing millions of transistors on a single chip. Because of advancements in VLSI design technologies, ICs are getting smaller, faster in speed and more efficient, making personal devices handy, and with more features. In this thesis work an interactive framework is designed in which the fundame… more
Date: August 2014
Creator: Battina, Brahmasree
Partner: UNT Libraries
open access

Low-loss LIGA-micromachined conductor-backed coplanar waveguide.

Description: A mesoscale low-loss LIGA-micromachined conductor-backed coplanar waveguide is presented. The 517 {micro}m lines are the tallest uniplanar LIGA-fabricated microwave transmission lines to date, as well as the first to be constructed of copper rather than nickel. The conductor-backed micromachined CPW on quartz achieves a measured attenuation of 0.064 dB/cm at 15.5 GHz.
Date: December 1, 2004
Creator: Forman, Michael A.
Partner: UNT Libraries Government Documents Department
open access

Microstructure Studies of Silicon-on-Insulator for Very Large Scale Integrated Circuit Applications

Description: Silicon-on-insulator formed by high dose oxygen ion implantation and subsequent epitaxially grown silicon layers were studied and compared with silicon on sapphire materials. Czochralski grown, (100) silicon wafers were implanted with molecular oxygen ions, 0+2, to a total dose of 2.12 x 10^18 0+/cm^2 at an energy of 150 keV/atom.
Date: December 1982
Creator: Hamdi, Aboud Helal
Partner: UNT Libraries
open access

Linear Amplifiers

Description: Problems in the design of linear amplifiers are presented from the point of view of the radio engineer.
Date: September 7, 1949
Creator: Schultz, M. A.
Partner: UNT Libraries Government Documents Department
open access

Columbia Scaling Circuits

Description: Abstract: "The advantages of high scaling ratios in counting random pulses are discussed. The mechanism of the basic circuit used in the Columbia University scaling circuits is described. The difficulties experienced in the performance of the earlier circuits are indicated and modified circuits to eliminate these difficulties are given. Precautions that must be observed in carrying out the constructional details are suggested. The complete circuit and specifications are given in detail for a Sc… more
Date: May 2, 1944
Creator: Glassford, H. A. & Dunning, J. R.
Partner: UNT Libraries Government Documents Department
open access

Capacitor mismatch caused by oxide thickness variations in submicron I. C. processes

Description: Chip design in submicron processes will present new challenges and problems which were not present in designs with larger dimension processes. One effect in the newer processes is the field oxide thickness variation due to interconnect density variations. This effect becomes much more extreme for the smaller dimension processes. Large density discontinuities can cause lower yield and will also result in capacitor value mismatch over substantial distances from the edges of a large array when usi… more
Date: May 4, 1999
Creator: Zimmerman, Tom
Partner: UNT Libraries Government Documents Department
open access

Performance of the CLAS12 Silicon Vertex Tracker modules

Description: For the 12 GeV upgrade, the CLAS12 experiment has designed a Silicon Vertex Tracker (SVT) using single sided microstrip sensors fabricated by Hamamatsu. The sensors have graded angle design to minimize dead areas and a readout pitch of 156{micro}m, with intermediate strip. Double sided SVT module hosts three daisy-chained sensors on each side with a full strip length of 33 cm. There are 512 channels per module read out by four Fermilab Silicon Strip Readout (FSSR2) chips featuring data driven a… more
Date: December 1, 2013
Creator: Antonioli, Mary Ann; Boiarinov, Serguie; Bonneau, Peter R.; Elouadrhiri, Latifa; Eng, Brian J.; Gotra, Yuri N. et al.
Partner: UNT Libraries Government Documents Department
open access

Deep Trek High Temperature Electronics Project

Description: This report summarizes technical progress achieved during the cooperative research agreement between Honeywell and U.S. Department of Energy to develop high-temperature electronics. Objects of this development included Silicon-on-Insulator (SOI) wafer process development for high temperature, supporting design tools and libraries, and high temperature integrated circuit component development including FPGA, EEPROM, high-resolution A-to-D converter, and a precision amplifier.
Date: July 31, 2007
Creator: Ohme, Bruce
Partner: UNT Libraries Government Documents Department
open access

Determining Two-Port S-Parameters from a One-Port Measurement Using a Novel Impedance-State Test Chip

Description: A novel custom high-speed test chip and data reduction technique that allows for the accurate determination of the two-port S-parameters of a passive network from a set of one-port measurements is presented. A typical application for this technique is high-speed integrated circuit package characterization where one-port is of a microelectronic size scale and inside the package. The test chip is designed to operate up to 20 GHz.
Date: March 4, 1999
Creator: Hietala, V.M.
Partner: UNT Libraries Government Documents Department
open access

Advanced modeling and simulation to design and manufacture high performance and reliable advanced microelectronics and microsystems.

Description: An interdisciplinary team of scientists and engineers having broad expertise in materials processing and properties, materials characterization, and computational mechanics was assembled to develop science-based modeling/simulation technology to design and reproducibly manufacture high performance and reliable, complex microelectronics and microsystems. The team's efforts focused on defining and developing a science-based infrastructure to enable predictive compaction, sintering, stress, and th… more
Date: July 1, 2007
Creator: Nettleship, Ian; Hinklin, Thomas; Holcomb, David Joseph; Tandon, Rajan; Arguello, Jose Guadalupe, Jr.; Dempsey, James Franklin et al.
Partner: UNT Libraries Government Documents Department
open access

FRONT-END ASIC FOR A SILICON COMPTON TELESCOPE.

Description: We describe a front-end application specific integrated circuit (ASIC) developed for a silicon Compton telescope. Composed of 32 channels, it reads out signals in both polarities from each side of a Silicon strip sensor, 2 mm thick 27 cm long, characterized by a strip capacitance of 30 pF. Each front-end channel provides low-noise charge amplification, shaping with a stabilized baseline, discrimination, and peak detection with an analog memory. The channels can process events simultaneously, an… more
Date: October 27, 2007
Creator: DE GERONIMO,G.; FRIED, J.; FROST, E.; PHLIPS, B.; VERNON, E. & WULF, E.A.
Partner: UNT Libraries Government Documents Department
open access

Finline Diode Six-Port: Fundamentals and Design Information

Description: Abstract: The preliminary design and testing of a planar circuit six-port with diode detectors is described. The planar circuit medium was chosen to be finline, and all preliminary work was done in WR-42 waveguide (18-26.5 GHz). The finline substrate was alumina, and initially commercial beam-lead diodes were bonded to the finline metalization. The goal is to design an integrated circuit which could be fabricated on one chip (with diode detectors) and used as part of a six port network analyzer… more
Date: December 1985
Creator: Weidman, Manly P.
Partner: UNT Libraries Government Documents Department
open access

Adaptive optics for improved retinal surgery and diagnostics

Description: It is now possible to field a compact adaptive optics (AO) system on a surgical microscope for use in retinal diagnostics and surgery. Recent developments in integrated circuit technology and optical photonics have led to the capability of building an AO system that is compact and significantly less expensive than traditional AO systems. It is foreseen that such an AO system can be integrated into a surgical microscope while maintaining a package size of a lunchbox. A prototype device can be de… more
Date: August 21, 2000
Creator: Humayun, M. S.; Sadda, S. R.; Thompson, C. A.; Olivier, S. S. & Kartz, M. W.
Partner: UNT Libraries Government Documents Department
open access

Implications of intelligent, integrated microsystems for product design and development

Description: Intelligent, integrated microsystems combine some or all of the functions of sensing, processing information, actuation, and communication within a single integrated package, and preferably upon a single silicon chip. As the elements of these highly integrated solutions interact strongly with each other, the microsystem can be neither designed nor fabricated piecemeal, in contrast to the more familiar assembled products. Driven by technological imperatives, microsystems will best be developed b… more
Date: April 19, 2000
Creator: MYERS,DAVID R. & MCWHORTER,PAUL J.
Partner: UNT Libraries Government Documents Department
open access

Extreme Ultraviolet Lithography for 0.1 {micro}m Devices

Description: Extreme Ultraviolet Lithography (EUVL) has emerged as one of the leading successors to optics for 0.1 {micro}m IC fabrication. Its strongest attribute is the potential to scale to much finer resolution at high throughput. As such, this technique could meet the lithography needs for Si ULSI down to fundamental device limits. In the US, Lawrence Livermore, Sandia, and Lawrence Berkeley National Laboratories are participating in an industry funded research effort to evolve EUV technology and build… more
Date: July 7, 1999
Creator: Vaidya, S.; Sweeney, D.W.; Stulen, R. & Attwood, D.
Partner: UNT Libraries Government Documents Department
open access

Failure analysis: Status and future trends

Description: Failure analysis is a critical element in the integrated circuit manufacturing industry. This paper reviews the changing role of failure analysis and describes major techniques employed in the industry today. Several advanced failure analysis techniques that meet the challenges imposed by advancements in integrated circuit technology are described and their applications are discussed. Future trends in failure analysis needed to keep pace with the continuing advancements in integrated circuit te… more
Date: February 1, 1995
Creator: Anderson, R. E.; Soden, J. M. & Henderson, C. L.
Partner: UNT Libraries Government Documents Department
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