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Charge Collection Studies on Integrated Circuit Test Structures using Heavy-Ion Microbeams and MEDICI Simulation Calculations

Description: Ion induced charge collection dynamics within Integrated Circuits (ICs) is important due to the presence of ionizing radiation in the IC environment. As the charge signals defining data states are reduced by voltage and area scaling, the semiconductor device will naturally have a higher susceptibility to ionizing radiation induced effects. The ionizing radiation can lead to the undesired generation and migration of charge within an IC. This can alter, for example, the memory state of a bit, and thereby produce what is called a "soft" error, or Single Event Upset (SEU). Therefore, the response of ICs to natural radiation is of great concern for the reliability of future devices. Immunity to soft errors is listed as a requirement in the 1997 National Technology Roadmap for Semiconductors prepared by the Semiconductor Industry Association in the United States. To design more robust devices, it is essential to create and test accurate models of induced charge collection and transport in semiconductor devices. A heavy ion microbeam produced by an accelerator is an ideal tool to study charge collection processes in ICs and to locate the weak nodes and structures for improvement through hardening design. In this dissertation, the Ion Beam Induced Charge Collection (IBICC) technique is utilized to simulate recoil effects of ions in ICs. These silicon or light ion recoils are usually produced by the elastic scattering or inelastic reactions between cosmic neutrons or protons and the lattice atoms in ICs. Specially designed test structures were experimentally studied, using microbeams produced at Sandia National Laboratories. A new technique, Diffusion Time Resolved IBICC, is first proposed in this work to measure the average arrival time of the diffused charge, which can be related to the first moment (or the average time) of the arrival carrier density at the junction. A 2D device simulation ...
Date: May 2000
Creator: Guo, Baonian
Partner: UNT Libraries

Microstructure studies of silicon-on-insulator for very large scale integrated circuit applications

Description: Silicon-on-insulator formed by high dose oxygen ion implantation and subsequent epitaxially grown silicon layers were studied and compared with silicon on sapphire materials. Czochralski grown, (100) silicon wafers were implanted with molecular oxygen ions, 0+2, to a total dose of 2.12 x 10^18 0+/cm^2 at an energy of 150 keV/atom.
Date: December 1982
Creator: Hamdi, Aboud Helal
Partner: UNT Libraries

Capacitor mismatch caused by oxide thickness variations in submicron I. C. processes

Description: Chip design in submicron processes will present new challenges and problems which were not present in designs with larger dimension processes. One effect in the newer processes is the field oxide thickness variation due to interconnect density variations. This effect becomes much more extreme for the smaller dimension processes. Large density discontinuities can cause lower yield and will also result in capacitor value mismatch over substantial distances from the edges of a large array when using poly/metal capacitors. If good matching in this type of large area capacitor array is required, the only way to achieve this is to guarantee nearly constant metal/ poly density for at least 1500 microns (this distance will likely depend on the process) around the edges of the array. If the array boundary is close to the chip edge, then dummy capacitors should be placed up to the chip edge, and another layout with similar density must be placed as close as possible to the relevant edges of the chip in the reticle. When using a standard MOSIS reticle size, this may entail placing dummy chip layouts around the chips of interest in order to guarantee that identical density exists for the required distance outside of any chip�s borders.
Date: May 4, 1999
Creator: Zimmerman, Tom
Partner: UNT Libraries Government Documents Department

Linear Amplifiers

Description: Problems in the design of linear amplifiers are presented from the point of view of the radio engineer.
Date: September 7, 1949
Creator: Schultz, M. A.
Partner: UNT Libraries Government Documents Department

Delay locked loop integrated circuit.

Description: This report gives a description of the development of a Delay Locked Loop (DLL) integrated circuit (IC). The DLL was developed and tested as a stand-alone IC test chip to be integrated into a larger application specific integrated circuit (ASIC), the Quadrature Digital Waveform Synthesizer (QDWS). The purpose of the DLL is to provide a digitally programmable delay to enable synchronization between an internal system clock and external peripherals with unknown clock skew. The DLL was designed and fabricated in the IBM 8RF process, a 0.13 {micro}m CMOS process. It was designed to operate with a 300MHz clock and has been tested up to 500MHz.
Date: October 1, 2007
Creator: Brocato, Robert Wesley
Partner: UNT Libraries Government Documents Department

Columbia Scaling Circuits

Description: Abstract: "The advantages of high scaling ratios in counting random pulses are discussed. The mechanism of the basic circuit used in the Columbia University scaling circuits is described. The difficulties experienced in the performance of the earlier circuits are indicated and modified circuits to eliminate these difficulties are given. Precautions that must be observed in carrying out the constructional details are suggested. The complete circuit and specifications are given in detail for a Scale of 128 for use with linear-amplifier systems" (p. 1).
Date: May 2, 1944
Creator: Glassford, H. A. & Dunning, J. R.
Partner: UNT Libraries Government Documents Department

An Efficient Hybrid Heuristic and Probabilistic Model for the Gate Matrix Layout Problem in VLSI Design

Description: In this thesis, the gate matrix layout problem in VLSI design is considered where the goal is to minimize the number of tracks required to layout a given circuit and a taxonomy of approaches to its solution is presented. An efficient hybrid heuristic is also proposed for this combinatorial optimization problem, which is based on the combination of probabilistic hill-climbing technique and greedy method. This heuristic is tested experimentally with respect to four existing algorithms. As test cases, five benchmark problems from the literature as well as randomly generated problem instances are considered. The experimental results show that the proposed hybrid algorithm, on the average, performs better than other heuristics in terms of the required computation time and/or the quality of solution. Due to the computation-intensive nature of the problem, an exact solution within reasonable time limits is impossible. So, it is difficult to judge the effectiveness of any heuristic in terms of the quality of solution (number of tracks required). A probabilistic model of the gate matrix layout problem that computes the expected number of tracks from the given input parameters, is useful to this respect. Such a probabilistic model is proposed in this thesis, and its performance is experimentally evaluated.
Date: August 1993
Creator: Bagchi, Tanuj
Partner: UNT Libraries

A Materials Approach to Silicon Wafer Level Contamination Issues from the Wet Clean Process

Description: Semiconductor devices are built using hyperpure silicon and very controlled levels of doping to create desired electrical properties. Contamination can alter these precisely controlled electrical properties that can render the device non-functional or unreliable. It is desirable to determine what impurities impact the device and control them. This study consists of four parts: a) determination of acceptable SCI (Standard Clean 1) bath contamination levels using VPD-DSE-GFAAS (Vapor Phase Decomposition Droplet Surface Etching Graphite Furnace Atomic Absorption Spectroscopy), b) copper deposition from various aqueous HF solutions, c) anion contamination from fluoropolymers used in chemical handling and d) metallic contamination from fluoropolymers and polyethylene used in chemical handling. A technique was developed for the determination of metals on a silicon wafer source at low levels. These levels were then correlated to contamination levels in a SCI bath. This correlation permits the determination of maximum permissible solution contaminant levels. Copper contamination is a concern for depositing on the wafer surface from hydrofluoric acid solutions. The relationship between copper concentration on the wafer surface and hydrofluoric acid concentration was determined. An inverse relationship exists and was explained by differences in diffusion rates between the differing copper species existing in aqueous hydrofluoric acid solutions. Finally, sources of contamination from materials used in chemical handling was studied. The predominant anion contamination from fluoropolymers was found to be fluorides. Metallic contamination from fluoropolymers and polyethylene was also studied. The primary metal contamination comes from the actual fabrication of the polymer and not from the polymer resin.
Date: December 1996
Creator: Hall, Lindsey H. (Lindsey Harrison)
Partner: UNT Libraries

Final Technical Report - 300°C Capable Electronics Platform and Temperature Sensor System For Enhanced Geothermal Systems

Description: A silicon carbide (SiC) based electronic temperature sensor prototype has been demonstrated to operate at 300°C. We showed continuous operation of 1,000 hours with SiC operational amplifier and surface mounted discreet resistors and capacitors on a ceramic circuit board. This feasibility demonstration is a major milestone in the development of high temperature electronics in general and high temperature geothermal exploration and well management tools in particular. SiC technology offers technical advantages that are not found in competing technologies such as silicon-on-insulator (SOI) at high temperatures of 200°C to 300°C and beyond. The SiC integrated circuits and packaging methods can be used in new product introduction by GE Oil and Gas for high temperature down-hole tools. The existing SiC fabrication facility at GE is sufficient to support the quantities currently demanded by the marketplace, and there are other entities in the United States and other countries capable of ramping up SiC technology manufacturing. The ceramic circuit boards are different from traditional organic-based electronics circuit boards, but the fabrication process is compatible with existing ceramic substrate manufacturing. This project has brought high temperature electronics forward, and brings us closer to commercializing tools that will enable and reduce the cost of enhanced geothermal technology to benefit the public in terms of providing clean renewable energy at lower costs.
Date: November 30, 2012
Creator: Chen, Cheng-Po; Shaddock, David; Sandvik, Peter; Saia, Rich; Amita Patil, Alexey Vert & Zhang, Tan
Partner: UNT Libraries Government Documents Department

A signature analysis method for IC failure analysis

Description: A new method of signature analysis is presented and explained. This method of signature analysis can be based on either experiential knowledge of failure analysis, observed data, or a combination of both. The method can also be used on low numbers of failures or even single failures. It uses the Dempster-Shafer theory to calculate failure mechanism confidence. The model is developed in the paper and an example is given for its use. 9 refs., 5 figs., 9 tabs.
Date: October 1, 1996
Creator: Henderson, C.L. & Soden, J.M.
Partner: UNT Libraries Government Documents Department

Determining Two-Port S-Parameters from a One-Port Measurement Using a Novel Impedance-State Test Chip

Description: A novel custom high-speed test chip and data reduction technique that allows for the accurate determination of the two-port S-parameters of a passive network from a set of one-port measurements is presented. A typical application for this technique is high-speed integrated circuit package characterization where one-port is of a microelectronic size scale and inside the package. The test chip is designed to operate up to 20 GHz.
Date: March 4, 1999
Creator: Hietala, V.M.
Partner: UNT Libraries Government Documents Department

IC-Compatible Technologies for Optical MEMS

Description: Optical Micro Electro Mechanical Systems (Optical MEMS) Technology holds the promise of one-day producing highly integrated optical systems on a common, monolithic substrate. The choice of fabrication technology used to manufacture Optical MEMS will play a pivotal role in the size, functionality and ultimately the cost of optical Microsystems. By leveraging the technology base developed for silicon integrated circuits, large batches of routers, emitters, detectors and amplifiers will soon be fabricated for literally pennies per part. In this article we review the current status of technologies used for Optical MEMS, as well as fabrication technologies of the future, emphasizing manufacturable surface micromachining approaches to producing reliable, low-cost devices for optical communications applications.
Date: April 30, 1999
Creator: Krygowski, T.W. & Sniegowski, J.J.
Partner: UNT Libraries Government Documents Department

Design Space Exploration of Domain Specific CGRAs Using Crowd-sourcing

Description: CGRAs (coarse grained reconfigurable array architectures) try to fill the gap between FPGAs and ASICs. Over three decades, the research towards CGRA design has produced number of architectures. Each of these designs lie at different points on a line drawn between FPGAs and ASICs, depending on the tradeoffs and design choices made during the design of architectures. Thus, design space exploration (DSE) takes a very important role in the circuit design process. In this work I propose the design space exploration of CGRAs can be done quickly and efficiently through crowd-sourcing and a game driven approach based on an interactive mapping game UNTANGLED and a design environment called SmartBricks. Both UNTANGLED and SmartBricks have been developed by our research team at Reconfigurable Computing Lab, UNT. I present the results of design space exploration of domain-specific reconfigurable architectures and compare the results comparing stripe vs mesh style, heterogeneous vs homogeneous. I also compare the results obtained from different interconnection topologies in mesh. These results show that this approach offers quick DSE for designers and also provides low power architectures for a suite of benchmarks. All results were obtained using standard cell ASICs with 90 nm process.
Date: August 2014
Creator: Sistla, Anil Kumar
Partner: UNT Libraries

Implications of intelligent, integrated microsystems for product design and development

Description: Intelligent, integrated microsystems combine some or all of the functions of sensing, processing information, actuation, and communication within a single integrated package, and preferably upon a single silicon chip. As the elements of these highly integrated solutions interact strongly with each other, the microsystem can be neither designed nor fabricated piecemeal, in contrast to the more familiar assembled products. Driven by technological imperatives, microsystems will best be developed by multi-disciplinary teams, most likely within the flatter, less hierarchical organizations. Standardization of design and process tools around a single, dominant technology will expedite economically viable operation under a common production infrastructure. The production base for intelligent, integrated microsystems has elements in common with the mathematical theory of chaos. Similar to chaos theory, the development of microsystems technology will be strongly dependent on, and optimized to, the initial product requirements that will drive standardization--thereby further rewarding early entrants to integrated microsystem technology.
Date: April 19, 2000
Partner: UNT Libraries Government Documents Department

A practical implementation of BICS for safety-critical applications

Description: This paper presents the challenges and solutions of applying Built-In-Current Sensors (BICS) to a safety-critical IC design for the purpose of in-situ state-of-health monitoring. The developed Quiscent Current Monitor (QCM) system consists of multiple BISC and digital control logic. The QCM BICS can detect leakage current as low as 4 {micro}A, run at system speed, and has relatively low real estate overhead. The QCM digital logic incorporates extensive debug capability and Built-In-Self-Test (BIST). The authors performed analog and digital simulations of the integrated BICS, and performed layout and tapeout of the design. Silicon is now in fabrication. Results to date show that, for some systems, BICS can be a practical and relatively inexpensive method for providing state-of-health monitoring of safety-critical microelectronics.
Date: February 9, 2000
Partner: UNT Libraries Government Documents Department

Extreme Ultraviolet Lithography for 0.1 {micro}m Devices

Description: Extreme Ultraviolet Lithography (EUVL) has emerged as one of the leading successors to optics for 0.1 {micro}m IC fabrication. Its strongest attribute is the potential to scale to much finer resolution at high throughput. As such, this technique could meet the lithography needs for Si ULSI down to fundamental device limits. In the US, Lawrence Livermore, Sandia, and Lawrence Berkeley National Laboratories are participating in an industry funded research effort to evolve EUV technology and build a prototype camera for lithographic exposure. More recently, both Europe and Japan have initiated government/industry sponsored programs in EUVL development. This talk will focus on our program successes to date, and highlight some of the challenges that still lie ahead.
Date: July 7, 1999
Creator: Vaidya, S.; Sweeney, D.W.; Stulen, R. & Attwood, D.
Partner: UNT Libraries Government Documents Department

Finline Diode Six-Port: Fundamentals and Design Information

Description: Abstract: The preliminary design and testing of a planar circuit six-port with diode detectors is described. The planar circuit medium was chosen to be finline, and all preliminary work was done in WR-42 waveguide (18-26.5 GHz). The finline substrate was alumina, and initially commercial beam-lead diodes were bonded to the finline metalization. The goal is to design an integrated circuit which could be fabricated on one chip (with diode detectors) and used as part of a six port network analyzer in the waveguide bands above 18 GHz. Initial designs proved to b unsatisfactory because of high losses and reflections. Most of the problems have b en solved, and a usable integrated finline circuit is a good possibility for a millimeter wave six-port.
Date: December 1985
Creator: Weidman, Manly P.
Partner: UNT Libraries Government Documents Department


Description: We describe a front-end application specific integrated circuit (ASIC) developed for a silicon Compton telescope. Composed of 32 channels, it reads out signals in both polarities from each side of a Silicon strip sensor, 2 mm thick 27 cm long, characterized by a strip capacitance of 30 pF. Each front-end channel provides low-noise charge amplification, shaping with a stabilized baseline, discrimination, and peak detection with an analog memory. The channels can process events simultaneously, and the read out is sparsified. The charge amplifier makes uses a dual-cascode configuration and dual-polarity adaptive reset, The low-hysteresis discriminator and the multi-phase peak detector process signals with a dynamic range in excess of four hundred. An equivalent noise charge (ENC) below 200 electrons was measured at 30 pF, with a slope of about 4.5 electrons/pF at a peaking time of 4 {micro}s. With a total dissipated power of 5 mW the channel covers an energy range up to 3.2 MeV.
Date: October 27, 2007
Partner: UNT Libraries Government Documents Department

Deep Trek High Temperature Electronics Project

Description: This report summarizes technical progress achieved during the cooperative research agreement between Honeywell and U.S. Department of Energy to develop high-temperature electronics. Objects of this development included Silicon-on-Insulator (SOI) wafer process development for high temperature, supporting design tools and libraries, and high temperature integrated circuit component development including FPGA, EEPROM, high-resolution A-to-D converter, and a precision amplifier.
Date: July 31, 2007
Creator: Ohme, Bruce
Partner: UNT Libraries Government Documents Department

Failure analysis: Status and future trends

Description: Failure analysis is a critical element in the integrated circuit manufacturing industry. This paper reviews the changing role of failure analysis and describes major techniques employed in the industry today. Several advanced failure analysis techniques that meet the challenges imposed by advancements in integrated circuit technology are described and their applications are discussed. Future trends in failure analysis needed to keep pace with the continuing advancements in integrated circuit technology are anticipated.
Date: February 1, 1995
Creator: Anderson, R. E.; Soden, J. M. & Henderson, C. L.
Partner: UNT Libraries Government Documents Department

Adaptive optics for improved retinal surgery and diagnostics

Description: It is now possible to field a compact adaptive optics (AO) system on a surgical microscope for use in retinal diagnostics and surgery. Recent developments in integrated circuit technology and optical photonics have led to the capability of building an AO system that is compact and significantly less expensive than traditional AO systems. It is foreseen that such an AO system can be integrated into a surgical microscope while maintaining a package size of a lunchbox. A prototype device can be developed in a manner that lends itself well to large-scale manufacturing.
Date: August 21, 2000
Creator: Humayun, M S; Sadda, S R; Thompson, C A; Olivier, S S & Kartz, M W
Partner: UNT Libraries Government Documents Department

An Algorithm for the PLA Equivalence Problem

Description: The Programmable Logic Array (PLA) has been widely used in the design of VLSI circuits and systems because of its regularity, flexibility, and simplicity. The equivalence problem is typically to verify that the final description of a circuit is functionally equivalent to its initial description. Verifying the functional equivalence of two descriptions is equivalent to proving their logical equivalence. This problem of pure logic is essential to circuit design. The most widely used technique to solve the problem is based on Binary Decision Diagram or BDD, proposed by Bryant in 1986. Unfortunately, BDD requires too much time and space to represent moderately large circuits for equivalence testing. We design and implement a new algorithm called the Cover-Merge Algorithm for the equivalence problem based on a divide-and-conquer strategy using the concept of cover and a derivational method. We prove that the algorithm is sound and complete. Because of the NP-completeness of the problem, we emphasize simplifications to reduce the search space or to avoid redundant computations. Simplification techniques are incorporated into the algorithm as an essential part to speed up the the derivation process. Two different sets of heuristics are developed for two opposite goals: one for the proof of equivalence and the other for its disproof. Experiments on a large scale of data have shown that big speed-ups can be achieved by prioritizing the heuristics and by choosing the most favorable one at each iteration of the Algorithm. Results are compared with those for BDD on standard benchmark problems as well as on random PLAs to perform an unbiased way of testing algorithms. It has been shown that the Cover-Merge Algorithm outperforms BDD in nearly all problem instances in terms of time and space. The algorithm has demonstrated fairly stabilized and practical performances especially for big PLAs under a wide ...
Date: December 1995
Creator: Moon, Gyo Sik
Partner: UNT Libraries