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FASTBUS Segment Driver microcode description

Description: The FASTBUS Segment Driver, hereafter referred to as the FSD, is a list-driven, microcoded interface between the UNIBUS of a PDP-11 system and the FASTBUS. The list structure used by the FSD allows the programmer on the PDP-11 to program a sequence of data transfers to take place without the aid or intervention of the PDP-11. This allows the FASTBUS to be driven at FSD rates, independent of the PDP-11 processor. Due to the difference in speed between the FASTBUS and UNIBUS, the major goal of the FSD was to provide an interface which could transfer data on FASTBUS without significantly reducing the bandwidth in a multi-master system. This was accomplished by bursting data on the FASTBUS through a 256 word fast buffer internal to the FSD. Data can be transferred at near FASTBUS rates through this memory and only moved on the UNIBUS when the FSD is not master of FASTBUS. This allows other masters in the same system to transfer their data while the FSD is moving data on the slower UNIBUS.
Date: June 1, 1983
Creator: Lesny, D.
Partner: UNT Libraries Government Documents Department

The bulk-store module for FASTBUS memory applications. Final technical report

Description: The FASTBUS system specification for high-energy physics and other data system applications defines a large address space in which support modules may reside on connected segments. Experiments in the physical sciences using FASTBUS indicate that the spectrum of support modules must continue to grow and be extended in capability. The features of the FASTBUS protocol can be effectively used to help increase the available data storage space and improve performance for large-memory configurations such as the Bulk-Store Module (BSM). To this end, the module design features automatic address-only histogramming, memory interleaving at the module level, and circular data buffering as well as normal random memory access. This report describes the components of the 32-bit, 8 megaword error-correcting memory module for the FASTBUS data system designed under a Phase II SBIR grant through the U.S. Department of Energy, Division of Energy Research. A key feature of the BSM is the design of a single-chip application-specific integrated circuit (ASIC) to interface the FASTBUS protocol to any slave application, and particularly to the BSM. The FASTBUS Slave Interface (FSI) design contains features that help the BSM perform its specified tasks, in addition to providing a complete interface to the FASTBUS protocol, including broadcast and advanced mode response. We further cover the chronology of the Phase II work effort and our experiences with two ASIC manufacturers in attempting to complete the actual fabrication of the FSI chips. The appendices of this report contains the functional description and design schematics of the BSM, and of the FSI ASICS in two different semiconductor technologies.
Date: February 1, 1996
Partner: UNT Libraries Government Documents Department

The Scalable Coherent Interface and related standards projects

Description: The Scalable Coherent Interface (SCI) project (IEEE P1596) found a way to avoid the limits that are inherent in bus technology. SCI provides bus-like services by transmitting packets on a collection of point-to-point unidirectional links. The SCI protocols support cache coherence in a distributed-shared-memory multiprocessor model, message passing, I/O, and local-area-network-like communication over fiber optic or wire links. VLSI circuits that operate parallel links at 1000 MByte/s and serial links at 1000 Mbit/s will be available early in 1992. Several ongoing SCI-related projects are applying the SCI technology to new areas or extending it to more difficult problems. P1596.1 defines the architecture of a bridge between SCI and VME; P1596.2 compatibly extends the cache coherence mechanism for efficient operation with kiloprocessor systems; P1596.3 defines new low-voltage (about 0.25 V) differential signals suitable for low power interfaces for CMOS or GaAs VLSI implementations of SCI; P1596.4 defines a high performance memory chip interface using these signals; P1596.5 defines data transfer formats for efficient interprocessor communication in heterogeneous multiprocessor systems. This paper reports the current status of SCI, related standards, and new projects. 16 refs.
Date: September 1, 1991
Creator: Gustavson, D.B.
Partner: UNT Libraries Government Documents Department

IEEE P1596, a scalable coherent interface for GigaByte/sec multiprocessor applications

Description: IEEE P1596, the Scalable Coherent Interface (formerly known as SuperBus) is based on experience gained during the development of Fastbus (IEEE 960), Futurebus (IEEE 896.1) and other modern 32-bit buses. SCI goals include a minimum bandwidth of 1 GByte/sec per processor; efficient support of a coherent distributed-cache image of shared memory; and support for segmentation, bus repeaters and general switched interconnections like Banyan, Omega, or full crossbar networks. To achieve these ambitious goals, SCI must sacrifice the immediate handshake characteristic of the present generation of buses in favor of a packet-like split-cycle protocol. Wire-ORs, broadcasts, and even ordinary passive bus structures are to be avoided. However, a lower performance (1 GByte/sec per backplane instead of per processor) implementation using a register insertion ring architecture on a passive ''backplane'' appears to be possible using the same interface as for the more costly switch networks. This paper presents a summary of current directions, and reports the status of the work in progress.
Date: November 1, 1988
Creator: Gustavson, D.B.
Partner: UNT Libraries Government Documents Department

What`s new with FASTBUS and what`s it done in the particle accelerator laboratories

Description: The FASTBUS modular high-speed data acquisition and control system has been described in earlier papers. Implementations have since been made in accelerator laboratories world-wide resulting in clarifications, modifications and extensions. Of tremendous benefit to users have been FASTBUS Standard Routines. The availability of such standard software is unique for high speed bus systems and resulted from the involvement of hardware and software specialists in all aspects of the development. FASTBUS is the highest performance instrumentation and data acquisition bus in existence and its development was essential to handle the outputs of detectors used with high energy accelerators now in operation. It has been an important factor in recent experiments, including the Z{sup 0} measurements at CERN, Fermilab and SLAC. Also among numerous FASTBUS implementations are those for TPC systems at KEK and BNL. 2 refs., 5 figs.
Date: December 31, 1991
Creator: Costrell, L.; Dawson, W. K.; Ponting, P. J.; Platner, E. D.; Paffrath, L.; Barsotti, E. J. et al.
Partner: UNT Libraries Government Documents Department

FASTBUS review 1985

Description: The progress of developments based on the FASTBUS Specification DOE/ER-0189 for modular high-speed data acquisition and control systems is reviewed. Available hardware components and efforts in standardized FASTBUS software are summarized. The status of FASTBUS applications at research laboratories in North America is reported. FASTBUS work in Europe and Japan is presented in other papers at this conference. Due to the highly condensed nature of this review, background information and references from reports at the 1983 and 1984 Nuclear Science Symposia may be useful. 17 refs., 4 figs.
Date: September 1, 1985
Creator: Walz, H.V. & Barsotti, E.J.
Partner: UNT Libraries Government Documents Department

FASTBUS for the particle accelerator laboratories

Description: The FASTBUS modular high speed data acquisition and control system for high energy physics and other applications was described by Costrell and Dawson at the 1983 Particle Accelerator Conference. Both the specification and the implementation of this interlaboratory development have progressed considerably since that time. Because of its many attractive features, FASTBUS is currently in use in several major nuclear and high energy physics laboratories and is also finding application in other areas. 10 refs.
Date: May 1, 1985
Creator: Dawson, W.K.; Costrell, L.; Ikeda, H.; Ponting, P.J. & Walz, H.V.
Partner: UNT Libraries Government Documents Department

The RISC processor module for FASTBUS computation applications. Final technical report

Description: The FASTBUS system specification for high-energy physics and other data-system applications anticipates the use of multiple, high-performance processor modules for data control and event reduction associated with experiments in the physical sciences. Existing processor designs will be unable to cope with the projected data-reduction and event-handling requirements of the complex experiments planned for the next generation of particle accelerators. Data-handling strategies for experimental physics are evolving from systems based upon a single central computer to those with arrays of high-speed, sophisticated, front-end processing elements. The advent of accelerators such as LEP and LHC, and beyond, is forcing the architecture of these processors toward the simpler RISC designs to enhance both speed and the software-development issue. This report describes the prototype development of a FASTBUS RISC Processor Module (FRPM) for use as a standard processing element in FASTBUS data-acquisition systems under a Phase II SBIR grant through the U.S. Department of Energy, Division of Energy Research. The FRPM hosts a reduced instruction set computer--the SPARCengine-2 by Sun Microcomputer Systems, Inc.--capable of executing 4.2 million floating point instructions per second with a clock of up to 40 MHz. The prototype FRPM supports a port to the FASTBUS crate segment by way of a standard-logic interface. The FRPM processor operates under a commercially available real-time operating system, and application software can be developed on workstation and mainframe computer systems. We further cover the chronology of the Phase II work, a discussion of the objectives, and our experiences with an ASIC manufacturer in attempting to complete the fabrication of a chip implementing the FASTBUS Master Interface (FMI).
Date: February 1, 1996
Partner: UNT Libraries Government Documents Department

FEREAD: Front End Readout software for the Fermilab PAN-DA data acquisition system

Description: The FEREAD system provides a multi-tasking framework for controlling the execution of experiment specific front end readout processes. It supports initializing the front end data acquisition hardware, queueing and processing readout activation signals, cleaning up at the end of data acquisition, and transferring configuration parameters and statistical data between a ''Host'' computer and the readout processes. FEREAD is implemented as part of the PAN-DA software system and is designed to run on any Motorola 68k based processor board. It has been ported to the FASTBUS General Purpose Master (GPM) interface board and the VME MVME133A processor board using the pSOS/Microtec environment. 12 refs., 2 figs.
Date: May 1, 1989
Creator: Dorries, T.; Haire, M.; Moore, C.; Pordes, R. & Votava, M.
Partner: UNT Libraries Government Documents Department

A real time integrated environment for Motorola 680xx-based VME and FASTBUS modules

Description: The Software Components Group pSOS operating system kernel and pROBE debugger have been extended to support the Fermilab PAN-DA system for a variety of Motorola 680xx-based VME and FASTBUS modules. These extensions include: a multi-tasking, reentrant implementation of Microtec C/Pascal; a serial port driver for terminal I/O and data transfer; a message reporting facility; and enhanced debugging tools. 5 refs., 1 fig.
Date: May 1, 1989
Creator: Berg, D.; Heinicke, P.; MacKinnon, B.; Nicinski, T. & Oleynik, G.
Partner: UNT Libraries Government Documents Department

Uniform communications software using TCP/IP

Description: Data acquisition applications at Fermilab require a reliable, distributed communication system for downloading, diagnostics, control, and data distribution. TCP/IP over Ethernet was chosen because of its uniform user interface and commercial availability for a number of processors and operating systems. This paper describes our software and hardware support for TCP/IP on VAX/VMS, VME/pSOS, FASTBUS/pSOS, and Unix systems. It includes plans to provide a portable, hardware independent implementation of TCP/IP based on Berkeley BSD software. 8 refs., 3 figs.
Date: May 1, 1989
Creator: Bernett, M. & Oleynik, G.
Partner: UNT Libraries Government Documents Department

32-Bit computer for large memory applications on FASTBUS

Description: A FASTBUS based 32-bit computer is being built at Los Alamos National Laboratory for use in systems requiring large fast memory in the FASTBUS environment. A separate local execution bus allows data reduction to proceed concurrently with other FASTBUS operations. The computer, which can operate in either master or slave mode, includes the National Semiconductor NS32032 chip set with demand paged memory management, floating point slave processor, interrupt control unit, timers, and time-of-day clock. The 16.0 megabytes of random access memory are interleaved to allow windowed direct memory access on and off the FASTBUS at 80 megabytes per second.
Date: January 1, 1985
Creator: Blossom, J.M.; Hong, J.P. & Kellner, R.G.
Partner: UNT Libraries Government Documents Department

Software for FASTBUS and Motorola 68K based readout controllers for data acquisition

Description: Many High Energy Physics experiments at Fermilab are now including FASTBUS front-ends in their data acquisition systems. The requirements on controllers to readout and control these FASTBUS systems are increasing in complexity and speed. The Data Acquisition Software group has designed general software for front end 68K processor boards housed in FASTBUS or VME to meet these needs. The first implementation has been developed for the General Purpose FASTBUS Master (GPM). This software is being ported to the FASTBUS Smart Crate Controller under development at Fermilab. The software is designed, using structured analysis tools and coding in C, to be easily portable in the future to new processor boards. As part of our extended support for FASTBUS, we have enhanced our software for the intelligent LeCroy 1821 FASTBUS interface and implemented the FASTBUS standard routines for the VAX/VMS operating system. 17 refs.
Date: May 1, 1989
Creator: Pordes, R.; Bernett, M.; Dorries, T.; Haire, M.; Moore, C.; Oleynik, G. et al.
Partner: UNT Libraries Government Documents Department

SLAC FASTBUS Snoop Module: test results and support software

Description: The development of a diagnostic module for FASTBUS has been completed. The Snoop Module is designed to reside on a Crate Segment and provide high-speed diagnostic monitoring and testing capabilities. Final hardware details and testing of production prototype modules are reported. Features of software under development for a stand-alone single Snoop diagnostic system and Multi-Snoop networks will be discussed. 3 refs., 2 figs.
Date: September 1, 1985
Creator: Gustavson, D.B. & Walz, H.V.
Partner: UNT Libraries Government Documents Department

FASTBUS interface for the 3081/E

Description: The design of a FASTBUS interface to the 3081/E is presented. The interface consists of two boards, one specific to FASTBUS, the other usable by other interfaces to the 3081/E. The FASTBUS board is a dual-ported slave, permitting access from either of two cable segments. The general purpose board supports transfers to and from 3081/E memory and provides control of program execution. It also has several features which facilitate software debugging.
Date: September 1, 1985
Creator: Barker, L.; Kunz, P.F.; Lankford, A.J.; Oxoby, G.; Paffrath, L.; Rankin, P. et al.
Partner: UNT Libraries Government Documents Department

Status of the SLAC SNOOP diagnostic module for FASTBUS

Description: A SNOOP Diagnostic Module for FASTBUS is under development at SLAC. The SNOOP Module resides on a FASTBUS crate segment and provides diagnostic monitoring and testing capability. It consists of a high-speed ECL front-end to monitor and single-step segment operations, a simple master interface, and a control processor with two serial communication ports. Module features and specifications are summrized, and prototype hardware is shown.
Date: March 1, 1983
Creator: Walz, H.V. & Gustavson, D.B.
Partner: UNT Libraries Government Documents Department

MWPC data acquisition in the Brookhaven FASTBUS

Description: For Brookhaven AGS Experiment No. 749, a data acquisition system to accommodate 12, 256 wire multiwire proportional chambers (MWPCs) has been built in the context of the Brookhaven FASTBUS. Information about wires hit or continuous clusters of wires hit is encoded as the centroids of the clusters and number of wires in those clusters. The encoded information is stored in a stack memory in a FASTBUS module where it can be accessed by a FASTBUS Master. Encoding time is less than 4 microseconds. Also, information (in the form of front panel outputs) as to the nature of the data is available in less than 200 nanoseconds.
Date: January 1, 1983
Creator: Black, J.K.; Blatt, S.R.; Campbell, M.C.; Kasha, H.; Schmidt, M.P.; Schwarz, C.B. et al.
Partner: UNT Libraries Government Documents Department

Brookhaven segment interconnect

Description: We have performed a high energy physics experiment using a multisegment Brookhaven FASTBUS system. The system was composed of three crate segments and two cable segments. We discuss the segment interconnect module which permits communication between the various segments.
Date: January 1, 1983
Creator: Morse, W.M.; Benenson, G.; Leipuner, L.B.; Larsen, R.C.; Black, J.K.; Blatt, S.R. et al.
Partner: UNT Libraries Government Documents Department

What's new with FASTBUS and what's it done in the particle accelerator laboratories

Description: The FASTBUS modular high-speed data acquisition and control system has been described in earlier papers. Implementations have since been made in accelerator laboratories world-wide resulting in clarifications, modifications and extensions. Of tremendous benefit to users have been FASTBUS Standard Routines. The availability of such standard software is unique for high speed bus systems and resulted from the involvement of hardware and software specialists in all aspects of the development. FASTBUS is the highest performance instrumentation and data acquisition bus in existence and its development was essential to handle the outputs of detectors used with high energy accelerators now in operation. It has been an important factor in recent experiments, including the Z{sup 0} measurements at CERN, Fermilab and SLAC. Also among numerous FASTBUS implementations are those for TPC systems at KEK and BNL. 2 refs., 5 figs.
Date: January 1, 1991
Creator: Costrell, L. (National Inst. of Standards and Technology, Gaithersburg, MD (United States)); Dawson, W.K. (British Columbia Univ., Vancouver, BC (Canada). TRIUMF Facility); Ponting, P.J. (European Organization for Nuclear Research, Geneva (Switzerland)); Platner, E.D.; Paffrath, L. (Brookhaven National Lab., Upton, NY (United States)) & Barsotti, E.J. (Fermi National Accelerator Lab., Batavia, IL (
Partner: UNT Libraries Government Documents Department

FASTBUS Diagnostic Language users manual. Version 3(74)

Description: FASTBUS Diagnostic Language (FDL) is an interactive interpretive language designed to aid the engineer or physicist/user in the testing and debugging of FASTBUS modules and systems. Since FASTBUS systems involve a variety of devices and data paths, it is frequently more efficient to utilize a high-level language system such as FDL for diagnostics, rather than to develop device-specific programs. FDL can also be used to a limited extent for both device control and data acquisition.
Date: July 1, 1983
Creator: Lesny, D.
Partner: UNT Libraries Government Documents Department

32-Bit FASTBUS computer

Description: Los Alamos National Laboratory is building a 32-bit FASTBUS computer using the NATIONAL SEMICONDUCTOR 32032 central processing unit (CPU) and containing 16 million bytes of memory. The board can act both as a FASTBUS master and as a FASTBUS slave. It contains a custom direct memory access (DMA) channel which can perform 80 million bytes per second block transfers across the FASTBUS.
Date: January 1, 1985
Creator: Blossom, J.M.; Hong, J.P. & Kellner, R.G.
Partner: UNT Libraries Government Documents Department

Introduction to FASTBUS

Description: FASTBUS is a standardized modular 32-bit data-bus system for performing data acquisition, data processing, and control in high energy physics and other applications. It has been developed by the Fast System Design Group of the U.S. NIM Committee. Presented here is an overview of the FASTBUS hardware specification, the operation of the FASTBUS protocol, the implications that the use of FASTBUS has for software systems, and some of the computer to FASTBUS interfaces developed to date.
Date: November 1, 1982
Creator: Logg, C.A.
Partner: UNT Libraries Government Documents Department