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Nodal Resistance Measurement System

Description: The latest development in the measurement techniques has resulted in fast improvements in the instruments used for measurement of various electrical quantities. A common problem in such instruments is the automation of acquiring, retrieving and controlling the measurements by a computer or a laptop. In this study, nodal resistance measurement (NRM) system is developed to solve the above problem. The purpose of this study is to design and develop a compact electronic board, which measures electrical resistance, and a computer or a laptop controls the board. For the above purpose, surface nodal points are created on the surface of the sample electrically conductive material. The nodal points are connected to the compact electronic board and this board is connected to the computer. The user selects the nodal points, from the computer, between which the NRM system measures the electrical resistance and displays the measured quantity on the computer.
Access: This item is restricted to the UNT Community Members at a UNT Libraries Location.
Date: May 2005
Creator: Putta, Sunil Kumar
Partner: UNT Libraries

Advanced High-Speed 16-Bit Digitizer System

Description: The fastest commercially available 16-bit ADC can only perform around 200 mega-samples per second (200 MS/s). Connecting ADC chips together in eight different time domains increases the quantity of samples taken by a factor of eight. This method of interleaving requires that the input signal being sampled is split into eight identical signals and arrives at each ADC chip at the same point in time. The splitting of the input signal is performed in the analog front end containing a wideband filter that impedance matches the input signal to the ADC chips. Each ADC uses a clock to tell it when to perform a conversion. Using eight unique clocks spaced in 45-degree increments is the method used to time shift when each ADC chip performs its conversion. Given that this control clock is a fixed frequency, the clock phase shifting is accomplished by tightly controlling the distance that the clock must travel, resulting in a time delay. The interleaved ADC chips will now generate digital data in eight different time domains. These data are processed inside a field-programmable gate array (FPGA) to move the data back into a single time domain and store it into memory. The FPGA also contains a Nios II processor that provides system control and data retrieval via Ethernet.
Date: May 1, 2012
Partner: UNT Libraries Government Documents Department

Design Space Exploration of Domain Specific CGRAs Using Crowd-sourcing

Description: CGRAs (coarse grained reconfigurable array architectures) try to fill the gap between FPGAs and ASICs. Over three decades, the research towards CGRA design has produced number of architectures. Each of these designs lie at different points on a line drawn between FPGAs and ASICs, depending on the tradeoffs and design choices made during the design of architectures. Thus, design space exploration (DSE) takes a very important role in the circuit design process. In this work I propose the design space exploration of CGRAs can be done quickly and efficiently through crowd-sourcing and a game driven approach based on an interactive mapping game UNTANGLED and a design environment called SmartBricks. Both UNTANGLED and SmartBricks have been developed by our research team at Reconfigurable Computing Lab, UNT. I present the results of design space exploration of domain-specific reconfigurable architectures and compare the results comparing stripe vs mesh style, heterogeneous vs homogeneous. I also compare the results obtained from different interconnection topologies in mesh. These results show that this approach offers quick DSE for designers and also provides low power architectures for a suite of benchmarks. All results were obtained using standard cell ASICs with 90 nm process.
Date: August 2014
Creator: Sistla, Anil Kumar
Partner: UNT Libraries

Sub-picosecond Resolution Time-to-Digital Converter

Description: Time-to-digital converters with sub-picosecond resolutions are needed to satisfy the requirements of time-on-flight measurements of the next generation of high energy and nuclear physics experiments. The converters must be highly integrated, power effective, low cost, and feature plug-and-play capabilities to handle the increasing number of channels (up to hundreds of millions) in future Department of Energy experiments. Current state-off-the-art time-to-digital converter integrated circuits do not have the sufficient degree of integration and flexibility to fulfill all the described requirements. During Phase I, the Advanced Science and Novel Technology Company in cooperation with the nuclear physics division of the Oak Ridge National Laboratory has developed the architecture of a novel time-to-digital converter with multiple channels connected to an external processor through a special interfacing block and synchronized by clock signals generated by an internal phase-locked loop. The critical blocks of the system including signal delay lines and delay-locked loops with proprietary differential delay cells, as well as the required digital code converter and the clock period counter have been designed and simulated using the advanced SiGe120 BiCMOS technological process. The results of investigations demonstrate a possibility to achieve the digitization accuracy within 1ps. ADSANTEC has demonstrated the feasibility of the proposed concept in computer simulations. The proposed system will be a critical component for the next generation of NEP experiments.
Date: March 30, 2006
Creator: Ph D, Vladimir Bratov; Ph D, Vladimir Katzman & MS EE, Jeb Binkley
Partner: UNT Libraries Government Documents Department

Improved Approach for Utilization of FPGA Technology into DAQ, DSP, and Computing Applications

Description: Innovation Partners proposed and successfully demonstrated in this SBIR Phase I grant a software/hardware co-design approach to reduce both the difficulty and time to implement Field Programmable Gate Array (FPGA) solutions to data acquisition and specialized computational applications. FPGAs can require excessive time for programming and require specialized knowledge that will be greatly reduced by the company's solution. Not only are FPGAs ideal for DAQ and embedded solutions, they can also be the best solution to specialized signal processing to replace Digital Signal Processors (DSPs). By allowing FPGA programming to be done in C with the equivalent of a simple compilation, algorithm changes and improvements can be implemented decreasing the life-cycle costs and allow subsitution of new FPGA designs staying above the technological details.
Date: January 28, 2009
Creator: Isenhower, Larry Donald
Partner: UNT Libraries Government Documents Department

A Verilog 8051 Soft Core for FPGA Applications

Description: The objective of this thesis was to develop an 8051 microcontroller soft core in the Verilog hardware description language (HDL). Each functional unit of the 8051 microcontroller was developed as a separate module, and tested for functionality using the open-source VHDL Dalton model as benchmark. These modules were then integrated to operate as concurrent processes in the 8051 soft core. The Verilog 8051 soft core was then synthesized in Quartus® II simulation and synthesis environment (Altera Corp., San Jose, CA, www.altera.com) and yielded the expected behavioral response to test programs written in 8051 assembler residing in the v8051 ROM. The design can operate at speeds up to 41 MHz and used only 16% of the FPGA fabric, thus allowing complex systems to be designed on a single chip. Further research and development can be performed on v8051 to enhance performance and functionality.
Date: August 2009
Creator: Rangoonwala, Sakina
Partner: UNT Libraries

FPGA Implementation of Low Density Party Check Codes Decoder

Description: Reliable communication over the noisy channel has become one of the major concerns in the field of digital wireless communications. The low density parity check codes (LDPC) has gained lot of attention recently because of their excellent error-correcting capacity. It was first proposed by Robert G. Gallager in 1960. LDPC codes belong to the class of linear block codes. Near capacity performance is achievable on a large collection of data transmission and storage.In my thesis I have focused on hardware implementation of (3, 6) - regular LDPC codes. A fully parallel decoder will require too high complexity of hardware realization. Partly parallel decoder has the advantage of effective compromise between decoding throughput and high hardware complexity. The decoding of the codeword follows the belief propagation alias probability propagation algorithm in log domain. A 9216 bit, (3, 6) regular LDPC code with code rate ½ was implemented on FPGA targeting Xilinx Virtex 4 XC4VLX80 device with package FF1148. This decoder achieves a maximum throughput of 82 Mbps. The entire model was designed in VHDL in the Xilinx ISE 9.2 environment.
Date: August 2009
Creator: Vijayakumar, Suresh
Partner: UNT Libraries

FPGA-based Upgrade to RITS-6 Control System, Designed with EMP Considerations

Description: The existing control system for the RITS-6, a 20-MA 3-MV pulsed-power accelerator located at Sandia National Laboratories, was built as a system of analog switches because the operators needed to be close enough to the machine to hear pulsed-power breakdowns, yet the electromagnetic pulse (EMP) emitted would disable any processor-based solutions. The resulting system requires operators to activate and deactivate a series of 110-V relays manually in a complex order. The machine is sensitive to both the order of operation and the time taken between steps. A mistake in either case would cause a misfire and possible machine damage. Based on these constraints, a field-programmable gate array (FPGA) was chosen as the core of a proposed upgrade to the control system. An FPGA is a series of logic elements connected during programming. Based on their connections, the elements can mimic primitive logic elements, a process called synthesis. The circuit is static; all paths exist simultaneously and do not depend on a processor. This should make it less sensitive to EMP. By shielding it and using good electromagnetic interference-reduction practices, it should continue to operate well in the electrically noisy environment. The FPGA has two advantages over the existing system. In manual operation mode, the synthesized logic gates keep the operators in sequence. In addition, a clock signal and synthesized countdown circuit provides an automated sequence, with adjustable delays, for quickly executing the time-critical portions of charging and firing. The FPGA is modeled as a set of states, each state being a unique set of values for the output signals. The state is determined by the input signals, and in the automated segment by the value of the synthesized countdown timer, with the default mode placing the system in a safe configuration. Unlike a processor-based system, any system stimulus that results ...
Date: July 1, 2009
Creator: Harold D. Anderson, John T. Williams
Partner: UNT Libraries Government Documents Department

FPGA Implementations of Elliptic Curve Cryptography and Tate Pairing over Binary Field

Description: Elliptic curve cryptography (ECC) is an alternative to traditional techniques for public key cryptography. It offers smaller key size without sacrificing security level. Tate pairing is a bilinear map used in identity based cryptography schemes. In a typical elliptic curve cryptosystem, elliptic curve point multiplication is the most computationally expensive component. Similarly, Tate pairing is also quite computationally expensive. Therefore, it is more attractive to implement the ECC and Tate pairing using hardware than using software. The bases of both ECC and Tate pairing are Galois field arithmetic units. In this thesis, I propose the FPGA implementations of the elliptic curve point multiplication in GF (2283) as well as Tate pairing computation on supersingular elliptic curve in GF (2283). I have designed and synthesized the elliptic curve point multiplication and Tate pairing module using Xilinx's FPGA, as well as synthesized all the Galois arithmetic units used in the designs. Experimental results demonstrate that the FPGA implementation can speedup the elliptic curve point multiplication by 31.6 times compared to software based implementation. The results also demonstrate that the FPGA implementation can speedup the Tate pairing computation by 152 times compared to software based implementation.
Date: August 2007
Creator: Huang, Jian
Partner: UNT Libraries

FPGA Prototyping of a Watermarking Algorithm for MPEG-4

Description: In the immediate future, multimedia product distribution through the Internet will become main stream. However, it can also have the side effect of unauthorized duplication and distribution of multimedia products. That effect could be a critical challenge to the legal ownership of copyright and intellectual property. Many schemes have been proposed to address these issues; one is digital watermarking which is appropriate for image and video copyright protection. Videos distributed via the Internet must be processed by compression for low bit rate, due to bandwidth limitations. The most widely adapted video compression standard is MPEG-4. Discrete cosine transform (DCT) domain watermarking is a secure algorithm which could survive video compression procedures and, most importantly, attacks attempting to remove the watermark, with a visibly degraded video quality result after the watermark attacks. For a commercial broadcasting video system, real-time response is always required. For this reason, an FPGA hardware implementation is studied in this work. This thesis deals with video compression, watermarking algorithms and their hardware implementation with FPGAs. A prototyping VLSI architecture will implement video compression and watermarking algorithms with the FPGA. The prototype is evaluated with video and watermarking quality metrics. Finally, it is seen that the video qualities of the watermarking at the uncompressed vs. the compressed domain are only 1dB of PSNR lower. However, the cost of compressed domain watermarking is the complexity of drift compensation for canceling the drifting effect.
Date: May 2007
Creator: Cai, Wei
Partner: UNT Libraries

Software and Hardware-In-The-Loop Modeling of an Audio Watermarking Algorithm

Description: Due to the accelerated growth in digital music distribution, it becomes easy to modify, intercept, and distribute material illegally. To overcome the urgent need for copyright protection against piracy, several audio watermarking schemes have been proposed and implemented. These digital audio watermarking schemes have the purpose of embedding inaudible information within the host file to cover copyright and authentication issues. This thesis proposes an audio watermarking model using MATLAB® and Simulink® software for 1K and 2K fast Fourier transform (FFT) lengths. The watermark insertion process is performed in the frequency domain to guarantee the imperceptibility of the watermark to the human auditory system. Additionally, the proposed audio watermarking model was implemented in a Cyclone® II FPGA device from Altera® using the Altera® DSP Builder tool and MATLAB/Simulink® software. To evaluate the performance of the proposed audio watermarking scheme, effectiveness and fidelity performance tests were conducted for the proposed software and hardware-in-the-loop based audio watermarking model.
Date: December 2010
Creator: Zarate Orozco, Ismael
Partner: UNT Libraries

Timing and Congestion Driven Algorithms for FPGA Placement

Description: Placement is one of the most important steps in physical design for VLSI circuits. For field programmable gate arrays (FPGAs), the placement step determines the location of each logic block. I present novel timing and congestion driven placement algorithms for FPGAs with minimal runtime overhead. By predicting the post-routing timing-critical edges and estimating congestion accurately, this algorithm is able to simultaneously reduce the critical path delay and the minimum number of routing tracks. The core of the algorithm consists of a criticality-history record of connection edges and a congestion map. This approach is applied to the 20 largest Microelectronics Center of North Carolina (MCNC) benchmark circuits. Experimental results show that compared with the state-of-the-art FPGA place and route package, the Versatile Place and Route (VPR) suite, this algorithm yields an average of 8.1% reduction (maximum 30.5%) in the critical path delay and 5% reduction in channel width. Meanwhile, the average runtime of the algorithm is only 2.3X as of VPR.
Date: December 2006
Creator: Zhuo, Yue
Partner: UNT Libraries

Interfacing Detectors to Triggers And DAQ Electronics

Description: The complete design of the front-end electronics interfacing LHCb detectors, Level-0 trigger and higher levels of trigger with flexible configuration parameters has been made for (a) ASIC implementation, and (b) FPGA implementation. The importance of approaching designs in technology-independent form becomes essential with the actual rapid electronics evolution. Being able to constrain the entire design to a few types of replicated components: (a) the fully programmable 3D-Flow system, and (b) the configurable front-end circuit described in this article, provides even further advantages because only one or two types of components will need to migrate to the newer technologies. To base on today's technology the design of a system such as the LHCb project that is to begin working in 2006 is not cost-effective. The effort required to migrate to a higher-performance will, in that case, be almost equivalent to completely redesigning the architecture from scratch. The proposed technology independent design with the current configurable front-end module described in this article and the scalable 3D-Flow fully programmable system described elsewhere, based on the study of the evolution of electronics during the past few years and the forecasted advances in the years to come, aims to provide a technology-independent design which lends itself to any technology at any time. In this case, technology independence is based mainly on generic-HDL reusable code which allows a very rapid realization of the state-of-the-art circuits in terms of gate density, power dissipation, and clock frequency. The design of four trigger towers presently fits into an OR3T30 FPGA. Preliminary test results (provided in this paper) meet the functional requirements of LHCb and provide sufficient flexibility to introduce future changes. The complete system design is also provided along with the integration of the front-end design in the entire system and the cost and dimension of the electronics.
Date: May 3, 1999
Creator: Crosetto, Dario B.
Partner: UNT Libraries Government Documents Department

High Performance Signal and Image Processing for Remote Sensing Using Reconfigurable Computers

Description: It is not uncommon for remote sensing systems to produce in excess of 100 Mbytes/sec. Los Alamos National Laboratory designed a reconfigurable computer to tackle the signal and image processing challenges of high bandwidth sensors. Reconfigurable computing, based on field programmable gate arrays, offers ten to one hundred times the performance of traditional microprocessors for certain algorithms. This paper discusses the architecture of the computer and the source of performance gains, as well as an example application. The calculation of multiple matched filters applied to multispectral imagery, showing a performance advantage of forty-five over Pentium II (450 MHz), is presented as an exemplar of algorithms appropriate for this technology.
Date: July 18, 1999
Creator: Caffrey, M.; Szymanski, J.J.; Begtrup, A.; Layne, J.; Nelson, T.; Robinson, S. et al.
Partner: UNT Libraries Government Documents Department

Applied Real-Time Integrated Distributed Control Systems: An Industrial Overview and an Implemented Laboratory Case Study

Description: This thesis dissertation mainly compares and investigates laboratory study of different implementation methodologies of applied control systems and how they can be adopted in industrial, as well as commercial, automation applications. Namely the research paper aims to assess or evaluate eventual feedback control loops' performance and robustness over multiple conventional or state-of-the-art technologies in the field of applied industrial automation and instrumentation by implementing a laboratory case study setup: the ball on beam system. Hence, the paper tries to close the gap between industry and academia by: first, conducting a historical study and background information of main evolutional and technological eras in the field of industrial process control automation and instrumentation. Then, some related basic theoretical as well as practical concepts are reviewed in Chapter 2 of the report before displaying the detailed design. After that, the next Chapter, analyses the ball on beam control system problem as the case studied in the context of this research through reviewing previous literature, modeling and simulation. The following Chapter details the proposed design and implementation of the ball on beam case study as if it is under the introduced distributed industrial automation architecture. Finally, Chapter 5 concludes this work by listing several points leaned, remarks, and observations, and stating possible development and the future vision of this research.
Date: August 2016
Creator: Zaitouni, Wael K
Partner: UNT Libraries

Survey of Field Programmable Gate Array Design Guides and Experience Relevant to Nuclear Power Plant Applications

Description: From a safety perspective, it is difficult to assess the correctness of FPGA devices without extensive documentation, tools, and review procedures. NUREG/CR-6463, "Review Guidelines on Software Languages for Use in Nuclear Power Plant Safety Systems," provides guidance to the Nuclear Regulatory Commission (NRC) on auditing of programs for safety systems written in ten high-level languages. A uniform framework for the formulation and discussion of language-specific programming guidelines was employed. Comparable guidelines based on a similar framework are needed for FPGA-based systems. The first task involves evaluation of regulatory experience gained by other countries and other agencies, and those captured in existing standards, to identify regulatory approaches that can be adopted by NRC. If existing regulations do not provide a sufficient regulatory basis for adopting relevant regulatory approaches that are uncovered, ORNL will identify the gaps. Information for this report was obtained through publicly available sources such as published papers and presentations. No proprietary information is represented.
Date: September 1, 2007
Creator: Bobrek, Miljko; Bouldin, Don; Holcomb, David Eugene; Killough, Stephen M; Smith, Stephen Fulton & Ward, Christina D
Partner: UNT Libraries Government Documents Department