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Simple PDP15 interface for the Versatec serial printer

Description: An interface was developed to go between the PDP 15/30 computer and the Versatec printer/plotter, model 200A, operating in the serial print mode. The interface construction involved fabricating a cable with two twisted pairs for a signal and a control line, speeding up the clock in the existing foreground teletype controller and changing less than a dozen wires in it. The associated I/ O device handler allows the printer to be used as the listing device in the Digital Equipment Corporation Advanced Monitor Software System. With the handler, the printer is capable of printing 80 character lines at approximately 120 lines per minute. (auth)
Date: January 1, 1974
Creator: Kosorok, J.R.
Partner: UNT Libraries Government Documents Department

Nova Branch-Driver operation

Description: The Branch Driver (13D) is the interface between a Nova or Supernova computer I/O and a multicrate CAMAC system. The manual discusses the operation and design specification of the BD and has a description of the instructions used. The complete set of non-CAMAC instructions for the BD is given. Programming examples for several types of modules and standard function codes for CAMAC are presented. A complete set of schematics is available, but is not included. (auth)
Date: October 1, 1973
Creator: Biswell, L.R. & Van Buren, D.T.
Partner: UNT Libraries Government Documents Department

XTOD - XES Interface Control Document

Description: This document describes the interface between the LCLS XTOD System (WBS No.1.5) and the LCLS XES (WBS No.1.6). The interface locations ranging from the beam dump to the far experimental hall are identified. Subsystems that connect at or cross the boundary are identified.
Date: September 7, 2005
Creator: Trent, J
Partner: UNT Libraries Government Documents Department

Adding memory to the PDP-9

Description: The University of Minnesota has expanded its PDP-9 memory to the full 32 K word capacity of the machine. The expansion from 8 K to 18 K words, entailing the construction of the Extended Memory Interface, was the most difficult part of the project. The interfacing procedure is described. (WHK)
Date: January 1, 1973
Creator: Marshak, M.L.
Partner: UNT Libraries Government Documents Department

A Simulation Study of the Virtual Interface Architecture

Description: The Virtual Interface Architecture (VIA) is an emerging standard for interconnecting commodity computing nodes into a cluster. Since VIA protocol. operations are implemented outside the operating system kernel (often, entirely in hardware), VIA transfers can be performed at very low delay, high throughput, and minimal CPU overhead. This makes VIA ideal when building large clusters that perform complex simulations of physical events, However, the scaling properties of VIA are less clear. This paper describes the design and results of a simulation model developed in OPNET to investigate VIA's ability to scale to clusters of> 1000 nodes.
Date: May 18, 1999
Creator: Hu, Tan Chang; Stans, Leonard & Tarman, Thomas D.
Partner: UNT Libraries Government Documents Department

A DSP based power electronics interface for alternate/renewable energy systems. Quarterly report 3.

Description: This report is an update on the research project involving the implementation of a DSP based power electronics interface for alternate/renewable energy systems that was funded by the Department of Energy under the Inventions and Innovations program 1998. The objective of this research is to develop a utility interface (dc to ac converter) suitable to interconnect alternate/renewable energy sources to the utility system. The DSP based power electronics interface in comparison with existing methods will excel in terms of efficiency, reliability and cost. Moreover DSP-based control provides the flexibility to upgrade/modify control algorithms to meet specific system requirements. The proposed interface will be capable of maintaining stiffness of the ac voltages at the point of common coupling regardless of variation in the input dc bus voltage. This will be achieved without the addition of any extra components to the basic interface topology but by inherently controlling the inverter switching strategy in accordance to the input voltage variation.
Date: March 31, 2000
Partner: UNT Libraries Government Documents Department

Scalable Parallel Utopia

Description: This contribution proposes a 128 bit wide interface structure clocked at approximately 80 MHz that will operate at 10 Gbps as a strawman for a 0C192C Utopia Specification. In addition, the concept of scalable width of data transfers in order to maintain manageably low clock rates is proposed.
Date: October 1, 1998
Creator: King, D. & Pierson, L.
Partner: UNT Libraries Government Documents Department

Overview of PV balance-of-systems technology: Experience and guidelines for utility ties in the United States of America

Description: The U.S. National Photovoltaic Program began in 1975 by supporting the development of terrestrial PV modules and hardware associated with grid-connected PV systems. Early PV-system demonstration programs were also supported and cost shared by the U.S. Department of Energy (DOE). A wide variety of PV systems were deployed, usually with utility participation. The early demonstration projects provided, and continue to provide, valuable PV system experience to utilities, designers and suppliers. As a result of experience gained, several important milestones in codes and standards pertaining to the design, installation and operation of photovoltaic (PV) systems have been completed. These code and standard activities were conducted through collaboration of participants from all sectors of the PV industry, utilities and the US DOE National Photovoltaic Program. Codes and standards that have been proposed, written, or modified include changes and additions for the 1999 National Electric Code{reg_sign} (NEC{reg_sign}), standards for fire and personnel safety, system testing, field acceptance, component qualification, and utility interconnection. Project authorization requests with the Institute of Electrical and Electronic Engineers (IEEE) have resulted in standards for component qualification and were further adapted for standards used to list PV modules and balance-of-system components. Industry collaboration with Underwriter Laboratories, Inc., with the American Society for Testing and Materials, and through critical input and review for international standards with the International Electrotechnical Commission have resulted in new and revised domestic and international standards for PV applications. Activities related to work on codes and standards through the International Energy Agency are also being supported by the PV industry and the US DOE. The paper shows relationships between activities in standards writing.
Date: October 1, 1997
Creator: Bower, W. & Whitaker, C.
Partner: UNT Libraries Government Documents Department

Low-power, parallel photonic interconnections for Multi-Chip Module applications

Description: New applications of photonic interconnects will involve the insertion of parallel-channel links into Multi-Chip Modules (MCMs). Such applications will drive photonic link components into more compact forms that consume far less power than traditional telecommunication data links. MCM-based applications will also require simplified drive circuitry, lower cost, and higher reliability than has been demonstrated currently in photonic and optoelectronic technologies. The work described is a parallel link array, designed for vertical (Z-Axis) interconnection of the layers in a MCM-based signal processor stack, operating at a data rate of 100 Mb/s. This interconnect is based upon high-efficiency VCSELs, HBT photoreceivers, integrated micro-optics, and MCM-compatible packaging techniques.
Date: December 31, 1994
Creator: Carson, R.F.; Lovejoy, M.L. & Lear, K.L.
Partner: UNT Libraries Government Documents Department

An object oriented software bus

Description: This paper describes a new approach to development of software for highly integrated software-hardware systems such as used for data acquisition and control. This approach, called the Object Oriented Software Bus (OSB), is a way to develop software according to a common specification similar to the way interface hardware has been developed since the advent of bus structures for minicomputers and microcomputers. Key concept of the OSB is extension of the common use of objects to support user interface and data analysis functions to the development of software objects that directly correspond to real- world hardware interfaces and modules.
Date: December 31, 1995
Creator: McGirt, F. & Wilkerson, J.F.
Partner: UNT Libraries Government Documents Department

Experiences in effective use of Tcl/Tk

Description: Tcl/Tk (Toot Command Language and Tool Kit, pronounced ``tickle tee-kay``) is a scripting language supporting Motifm style X Window interfaces. It is extendible, allowing developers to embed additional functionality as commands in the language. However, the power and flexibility of the system leads to many variations or possibilities in its usage. We describe effective methods for taking advantage of Tcl/Tk to increase productivity and enhance the flexibility and adaptability of applications: writing simple Tcl/Tk scripts, extending the Tcl/Tk widget set, wrapping Tcl commands around existing classes and functions, and building Tcl/Tk and 3GL coprocesses. Examples are presented from working applications.
Date: June 1, 1995
Creator: Lee, R.W.
Partner: UNT Libraries Government Documents Department

A standard interface for debugger access to message queue information in MPI.

Description: This paper discusses the design and implementation of an interface that allows a debugger to obtain the information necessary to display the contents of the MPI message queues. The design has been implemented in the TotalView debugger, and dynamic libraries that conform to the interface exist for MPICH, as well as the proprietary MPI implementations from Compaq, IBM, and SGI.
Date: June 25, 1999
Creator: Cownie, J. & W., Gropp.
Partner: UNT Libraries Government Documents Department

Infrastructure and interfaces for large-scale numerical software.

Description: The complexity of large-scale scientific simulations often necessitates the combined use of multiple software packages developed by different groups in areas such as adaptive mesh manipulations, scalable algebraic solvers, and optimization. Historically, these packages have been combined by using custom code. This practice inhibits experimentation with and comparison of multiple tools that provide similar functionality through different implementations. The ALICE project, a collaborative effort among researchers at Argonne National Laboratory, is exploring the use of component-based software engineering to provide better interoperability among numerical toolkits. They discuss some initial experiences in developing an infrastructure and interfaces for high-performance numerical computing.
Date: June 10, 1999
Creator: Freitag, L.; Gropp, W. D.; Hovland, P. D.; McInnes, L. C. & Smith, B. F.
Partner: UNT Libraries Government Documents Department

CAMAC Driver Support for Windows NT{trademark} and Lunux{trademark}

Description: CAMAC is a Modular Instrumentation and Digital Interface System defined as a standardized instrumentation system for Computer Automated Measurement and Control. CAMAC hardware and software has been defined by the NIM Committee (National Instrumentation Methods Committee) of the US Department of Energy and the ESONE Committee (European Standards on Nuclear Electronics Committee) of European Laboratories. Fermi National Accelerator Laboratory has for many years produced software packages that follow the ANSI/IEEE standard 758-1979 for a variety of computers, CAMAC controller interfaces, and operating systems. In order to enable the re-use of existing hardware and software, Fermilab now supports standard routine libraries and drivers for Windows NT 4.0 and the Linux operating systems for the Jorway 411s SCSI Bus CAMAC Driver[l] and the Jorway73A SCSI Bus CAMAC Crate Controller. A number of test stands and small experiments both on-site and off-site are using this software for their CAMAC data acquisition needs.
Date: July 27, 1999
Creator: Streets, D.A. Slimmer and J.M.
Partner: UNT Libraries Government Documents Department

Design and testing of a high power, ultra-high vacuum, dual-directional coupler for the Advanced Photon Source (APS) linear accelerator

Description: Leaks and cracks have developed in the vacuum windows of the linac WR 284 waveguide directional couplers. In the existing coupler design the vacuum window is brazed to the waveguide. Replacement of a cracked window requires the removal of the component from the waveguide system resulting in a loss of vacuum in the waveguide. A new design has been developed and a prototype tested that utilizes bolted-in vacuum windows and allows for easier replacement of the windows in the system, while still providing suitable radio frequency (rf) specifications.
Date: July 1, 1995
Creator: Brauer, S.O.; Grelick, A.E.; Grimmer, J.; Otocki, R.D.; Kang, Y.W.; Noonan, J. et al.
Partner: UNT Libraries Government Documents Department

Users manual for bfort: Producing Fortran interfaces to C source code

Description: In many applications, the most natural computer language to write in may be different from the most natural language to provide a library in. For example, many scientific computing applications are written in Fortran, while many software libraries-particularly those dealing with complicated data structures or dynamic memory management-are written in C. Providing an interface so that Fortran programs can call routines written in C can be a tedious and error-prone process. We describe here a tool that automatically generates a Fortran-callable wrapper for routines written in C, using only a small, structured comment and the declaration of the routine in C. This tool has been used on two large software packages, PETSc and the MPICH implementation of MPI.
Date: March 1, 1995
Creator: Gropp, W.
Partner: UNT Libraries Government Documents Department

A network architecture for Petaflops supercomputers.

Description: If we are to build a supercomputer with a speed of 10{sup 15} floating operations per second (1 PetaFLOPS), interconnect technology will need to be improved considerably over what it is today. In this report, we explore one possible interconnect design for such a network. The guiding principle in this design is the optimization of all components for the finiteness of the speed of light. To achieve a linear speedup in time over well-tested supercomputers of todays' designs will require scaling up of processor power and bandwidth and scaling down of latency. Latency scaling is the most challenging: it requires a 100 ns user-to-user latency for messages traveling the full diameter of the machine. To meet this constraint requires simultaneously minimizing wire length through 3D packaging, new low-latency electrical signaling mechanisms, extremely fast routers, and new network interfaces. In this report, we outline approaches and implementations that will meet the requirements when implemented as a system. No technology breakthroughs are required.
Date: September 1, 2003
Creator: DeBenedictis, Erik P.
Partner: UNT Libraries Government Documents Department