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Micromachined VLSI 3D electronics. Final report for period September 1, 2000 - March 31, 2001

Description: The phase I program investigated the construction of electronic interconnections through the thickness of a silicon wafer. The novel aspects of the technology are that the length-to-width ratio of the channels is as high as 100:1, so that the minimum amount of real estate is used for contact area. Constructing a large array of these through-wafer interconnections will enable two circuit die to be coupled on opposite sides of a silicon circuit board providing high speed connection between the two.
Date: March 31, 2001
Creator: Beetz, C.P.; Steinbeck, J. & Hsueh, K.L.
Partner: UNT Libraries Government Documents Department

Latch-up control in CMOS integrated circuits

Description: The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS-integrated circuit structures. Under normal bias, the parasitic SCR is in its blocking state but, if subjected to a large voltage spike or if exposed to an ionizing environment, triggering may occur. This may result in device burn-out or loss of state. The problem has been extensively studied for space and weapons applications. Prevention of latch-up has been achieved in conservative design (approx. 9 ..mu..m p-well depths) by the use of minority lifetime control methods such as gold doping and neutron irradiation and by modifying the base transport factor with buried layers. The push toward VLSI densities will enhance parasitic action sufficiently so that the problem will become of more universal concern. The paper will surveys latch-up control methods presently employed for weapons and space applications on present (approx. 9 ..mu..m p-well) CMOS and indicates the extent of their applicability to VLSI designs.
Date: July 13, 1979
Creator: Ochoa, A.; Dawes, W.; Estreich, D. & Packard, H.
Partner: UNT Libraries Government Documents Department

HMC-to-flatpack attachment

Description: A method has been developed for attaching a completed hybrid microcircuit to a flatpack which can then be hermetically sealed. Ablefilm 517B and Epo-Tek H77 epoxies, in conjunction with an abraded flatpack and applied pressure during cure, were shown to provide HMC-to-flatpack bonds which meet all environmental and processing requirements of hybrid microcircuits in two recent programs.
Date: April 1, 1978
Creator: Zawicki, L.R.
Partner: UNT Libraries Government Documents Department

Semiconductor die attachment. Final report

Description: A technique was established for attaching non-beam lead semiconductor devices to metallized ceramic substrates for hybrid microcircuits (HMCs). Conductive and non-conductive epoxies were shown to be capable of high shear strengths after exposure to high temperatures (125 to 200/sup 0/C) for significant periods of time (48 to 168 h). Chip-on-tab devices attached to the substrate with Ablefilm 517 non-conductive epoxy was the technology chosen.
Date: April 1, 1978
Creator: Zawicki, L.R.
Partner: UNT Libraries Government Documents Department

Process monitoring system

Description: An automated process monitoring and control concept applicable to printed wiring board fabrication has been generated. This conceptual system utilizes a minicomputer to provide improved process control by monitoring, analyzing, and controlling critical parameters and equipment associated with printed wring board production processes.
Date: March 1, 1979
Creator: Hoefer, J.J.
Partner: UNT Libraries Government Documents Department

Quad delay gate generator (LBL No. 21X6691 P-2)

Description: A quad delay gate generator has been designed and packaged in a single-width NIM module. Both delay times and gate widths may be set continuously from 25 ns to 120 ..mu..sec. In normal operation, the gate follows the delay time unless a ''stop'' pulse cuts it short. Alternatively, the module may be operated in a bipolar mode, where the delay time is set by the input ''start'' pulse and reset by the input ''stop'' pulse. Modes and coarse time ranges are set via an octal DIP switch on the front panel. Fine adjustments of the delay and gate width are made via two twenty-turn potentiometers. Stability over a several day period was measured at approx. 250 ps on the 120 ns full scale range. LEDs gives a visual indication of both the input rate and the dead time.
Date: August 1, 1986
Creator: McDonald, R.J.; Maier, M.R.; Landis, D.A. & Wozniak, G.J.
Partner: UNT Libraries Government Documents Department

Figure-of-merit for bare and coated wires and flat ribbon jumpers

Description: Wire and ribbon jumpers are often used in HMC's to bridge over other circuitry. A polymeric coating has been proposed for use as a stiffener under high acceleration loads. This work proposes a dimensionless Figure-of-Merit for jumpers and compares bare and coated jumers via classical mathematical models and through a Finite Element Method (FEM) model. Real production geometry, end attachment conditions, and acceleration direction factors are explicitly included in the FEM model. The results do not justify adding the coating.
Date: November 1, 1979
Creator: Heffley, P.M.
Partner: UNT Libraries Government Documents Department

Voltage-clearance recommendations for printed boards

Description: Present and future trends in printed board designs point to higher circuit densities with narrower lines and closer spacings. Some designers are now laying out boards with 0.13 mm lines and spacings. The reduction of nominal spacing between conductive elements has raised questions concerning the adequacy of present voltage-clearance recommendations. The present recommendations are considered too conservative in that they are weighted with large safety factors, especially for small clearances, and are frequently disregarded by many designers. Published voltage breakdown measurements made on printed boards with comb patterns with their enhanced conductor test lengths show breakdowns occurring at much higher voltages than those specified for the clearances in existing documents. A Task Group was set up to review published breakdown measurements and to make any additional measurements necessary to provide voltage-clearance recommendations. These recommendations are reported.
Date: January 1, 1980
Creator: Jennings, C.W.; Cave, G.; Evans, A.; Harrington, D.J.; Kirchenbaum, J.; Martz, R.E. et al.
Partner: UNT Libraries Government Documents Department

Circuit board routing attachment for Fermilab Gerber plotter

Description: A new and potentially important method of producing large circuit boards has been developed at Fermilab. A Gerber Flat Bed Plotter with an active area of 5' x 16' has been fitted with a machining head to produce a circuit board without the use of photography or chemicals. The modifications of the Gerber Plotter do not impair its use as a photoplotter or pen plotter, the machining head is merely exchanged with the standard attachments. The modifications to the program are minimal; this will be described in another report. The machining head is fitted with an air bearing motorized spindle driven at a speed of 40,000 rpm to 90,000 rpm. The spindle also is provided with air bearings on its outside diameter, offering frictionless vertical travel guidance. Vertical travel of the spindle is driven by a spring return single acting air cylinder. An adjustable hydraulic damper slows the spindle travel near the end of its downward stroke. Two programmable stops control spindle down stroke position, and limit switches are provided for position feedback to the control system. A vacuum system collects chips at the cutter head. No lubrication or regular maintenance is required. The circuit board to be fabricated is supported on a porous plastic mat which allows table vacuum to hold the board in place while allowing the cutters or drills to cut through the board without damaging the rubber platen of the plotter. The perimeter of the board must be covered to the limits of the table vacuum area used to prevent excessive leakage.
Date: May 10, 1984
Creator: Lindenmeyer, C.
Partner: UNT Libraries Government Documents Department

Microprocessor circuit monitor. Final report

Description: A new laboratory capability has been developed which will be used to support some microprocessor based products such as an electronic programmer. The monitor system allows the user to select samples from the instruction set of the microprocessor product under test and verify its progress through those instructions during a test run. The monitor records the time when each selected instruction is addressed and prints out a record of address and time data when a run is complete. These capabilities provide a significant diagnostic tool for investigating a microprocessor malfunction. As an example, the monitor system was successfully used to locate and identify a change that had been made to the instruction set of an electronic programmer. The monitor system is designed to test specific products. The concept, however, may be applied to other microprocessor based products.
Date: February 1, 1979
Creator: Stevens, D.J.
Partner: UNT Libraries Government Documents Department

Research, Commercialization, & Workforce Development in the Polymer/Electronics Recycling Industry

Description: The Mid-Atlantic Recycling Center for End-of-Life Electronics (MARCEE) was set up in 1999 in response to a call from Congressman Alan Mollohan, who had a strong interest in this subject. A consortium was put together which included the Polymer Alliance Zone (PAZ) of West Virginia, West Virginia University (WVU), DN American and Ecolibrium. The consortium developed a set of objectives and task plans, which included both the research issues of setting up facilities to demanufacture End-of-Life Electronics (EoLE), the economics of the demanufacturing process, and the infrastructure development necessary for a sustainable recycling industry to be established in West Virginia. This report discusses the work of the MARCEE Project Consortium from November 1999 through March 2005. While the body of the report is distributed in hard-copy form the Appendices are being distributed on CD's.
Date: February 1, 2006
Creator: Irwin, Carl; Gupta, Rakesh; Turton, Richard; Hota, GangaRao; Logar, Cyril; Ponzurick, Tom et al.
Partner: UNT Libraries Government Documents Department