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Pulse Amplifiers Using Transistor Circuits

Description: From Introduction: "The high frequency response remains important even when pulse shaping is introduced. Pulse shaping is used to improve the time resolution of the system, to minimize overload distortion, or to facilitate the action of discriminating and recording circuits. The amplifier response may be optimized by such shaping, but in general the overall characteristics will be fixed by the particular detector system."
Date: January 23, 1958
Creator: Graveson, R. T. & Sadowski, H.
Partner: UNT Libraries Government Documents Department

Transistorization of Nuclear Counting Circuits

Description: From Abstract: "The advantage of long operational life, low power drain and miniaturization may be realized in nuclear counting circuits through the use of transistors. The disadvantage of instability, due to the effects of temperature change in the transistor, may be minimized in counting circuit designs. Representative circuits of a binary stage, amplitude discriminator, one shot multivibrator, and ratemeters are included. These were designed using the criteria of an minimum Beta and a maximum Ico."
Date: August 19, 1957
Creator: Graveson, R. T. & Sadowski, H.
Partner: UNT Libraries Government Documents Department

A Digital Comparator

Description: A digital comparator has been designed to flag data which goes above a maximum limit or below a minimum limit.
Date: September 21, 1960
Creator: Bourgeois, N. A.
Partner: UNT Libraries Government Documents Department

Charge Collection Studies on Integrated Circuit Test Structures using Heavy-Ion Microbeams and MEDICI Simulation Calculations

Description: Ion induced charge collection dynamics within Integrated Circuits (ICs) is important due to the presence of ionizing radiation in the IC environment. As the charge signals defining data states are reduced by voltage and area scaling, the semiconductor device will naturally have a higher susceptibility to ionizing radiation induced effects. The ionizing radiation can lead to the undesired generation and migration of charge within an IC. This can alter, for example, the memory state of a bit, and thereby produce what is called a "soft" error, or Single Event Upset (SEU). Therefore, the response of ICs to natural radiation is of great concern for the reliability of future devices. Immunity to soft errors is listed as a requirement in the 1997 National Technology Roadmap for Semiconductors prepared by the Semiconductor Industry Association in the United States. To design more robust devices, it is essential to create and test accurate models of induced charge collection and transport in semiconductor devices. A heavy ion microbeam produced by an accelerator is an ideal tool to study charge collection processes in ICs and to locate the weak nodes and structures for improvement through hardening design. In this dissertation, the Ion Beam Induced Charge Collection (IBICC) technique is utilized to simulate recoil effects of ions in ICs. These silicon or light ion recoils are usually produced by the elastic scattering or inelastic reactions between cosmic neutrons or protons and the lattice atoms in ICs. Specially designed test structures were experimentally studied, using microbeams produced at Sandia National Laboratories. A new technique, Diffusion Time Resolved IBICC, is first proposed in this work to measure the average arrival time of the diffused charge, which can be related to the first moment (or the average time) of the arrival carrier density at the junction. A 2D device simulation ...
Date: May 2000
Creator: Guo, Baonian
Partner: UNT Libraries

Twin Channel Count Integrator (EH1-503)

Description: Report issued by the Brookhaven National Laboratory discussing a twin channel count integrator. As stated in the introduction, "an accurate and stable recording ratemeter, designed to present the data from two counters on one strip chart recorder, is described" (p. 1). This report includes tables, and illustrations.
Date: June 1956
Creator: Higinbotham, William A. & Tillinger, J.
Partner: UNT Libraries Government Documents Department

Latch-up control in CMOS integrated circuits

Description: The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS-integrated circuit structures. Under normal bias, the parasitic SCR is in its blocking state but, if subjected to a large voltage spike or if exposed to an ionizing environment, triggering may occur. This may result in device burn-out or loss of state. The problem has been extensively studied for space and weapons applications. Prevention of latch-up has been achieved in conservative design (approx. 9 ..mu..m p-well depths) by the use of minority lifetime control methods such as gold doping and neutron irradiation and by modifying the base transport factor with buried layers. The push toward VLSI densities will enhance parasitic action sufficiently so that the problem will become of more universal concern. The paper will surveys latch-up control methods presently employed for weapons and space applications on present (approx. 9 ..mu..m p-well) CMOS and indicates the extent of their applicability to VLSI designs.
Date: July 13, 1979
Creator: Ochoa, A.; Dawes, W.; Estreich, D. & Packard, H.
Partner: UNT Libraries Government Documents Department

Charts for rapid analysis of 45 degree strain-rosette data

Description: From Summary: "Charts are presented for rapidly determining the principal strains and stresses, the maximum shear strain and stress, and the orientation of principal axes from data on 45 degree strain rosettes. The charts may be used for analyzing the conventional data consisting of strains measured along three gage lines 45 degrees apart, but their application is more direct if the rosette data are obtained by means of special circuits that require the use of four gages 45 degrees apart."
Date: May 1944
Creator: Manson, S. S.
Partner: UNT Libraries Government Documents Department

An analytical and experimental study of the transient response of a pressure-regulating relief valve in a hydraulic circuit

Description: From Introduction: "This report presents an analysis of the response of the relief valve to sudden flow-demand changes. The analysis can be applied to the design of relief valves to satisfy given response specifications and to predict the stability of the valve in a specific hydraulic circuit. For this reason, derivatives of all the constants employed are included in the report."
Date: March 1954
Creator: Gold, Harold & Otto, Edward W.
Partner: UNT Libraries Government Documents Department

Upgrade of NSLS timing system

Description: We report on the progress of the new NSLS timing system. There are three types of requirements for NSLS timing system: clocks, synchronization and trigger circuits. All ring revolution frequency clocks are generated using ECL and high speed TTL logic. The synchronization circuits allows to fill both storage rings with any bunch pattern. The triggers are generated by using commercially available digital delay generators. The delay unit`s outputs are ultrastable, with a resolution of 5 ps, and are programmed by computer via IEEE 488 interface. The block diagrams, description of all major timing components and the present status are provided in this paper.
Date: May 1, 1995
Creator: Singh, O.; Ramamoorthy, S.; Sheehan, J. & Smith, J.
Partner: UNT Libraries Government Documents Department

Transistor Scintillation Spectrometer

Description: Report describing "an AC-operated portable scintillation spectrometer consisting of a preamplifier, a linear pulse amplifier, a single-channel pulse-height analyzer, a linear count-rate meter, a scaler, and a high-voltage power supply. The operation and performance of the circuits are discussed" (p. 3).
Date: February 1960
Creator: Strauss, Michael G.
Partner: UNT Libraries Government Documents Department

Process-Voltage-Temperature Aware Nanoscale Circuit Optimization

Description: Embedded systems which are targeted towards portable applications are required to have low power consumption because such portable devices are typically powered by batteries. During the memory accesses of such battery operated portable systems, including laptops, cell phones and other devices, a significant amount of power or energy is consumed which significantly affects the battery life. Therefore, efficient and leakage power saving cache designs are needed for longer operation of battery powered applications. Design engineers have limited control over many design parameters of the circuit and hence face many chal-lenges due to inherent process technology variations, particularly on static random access memory (SRAM) circuit design. As CMOS process technologies scale down deeper into the nanometer regime, the push for high performance and reliable systems becomes even more challenging. As a result, developing low-power designs while maintaining better performance of the circuit becomes a very difficult task. Furthermore, a major need for accurate analysis and optimization of various forms of total power dissipation and performance in nanoscale CMOS technologies, particularly in SRAMs, is another critical issue to be considered. This dissertation proposes power-leakage and static noise margin (SNM) analysis and methodologies to achieve optimized static random access memories (SRAMs). Alternate topologies of SRAMs, mainly a 7-transistor SRAM, are taken as a case study throughout this dissertation. The optimized cache designs are process-voltage-temperature (PVT) tolerant and consider individual cells as well as memory arrays.
Date: December 2010
Creator: Thakral, Garima
Partner: UNT Libraries

Microstructure studies of silicon-on-insulator for very large scale integrated circuit applications

Description: Silicon-on-insulator formed by high dose oxygen ion implantation and subsequent epitaxially grown silicon layers were studied and compared with silicon on sapphire materials. Czochralski grown, (100) silicon wafers were implanted with molecular oxygen ions, 0+2, to a total dose of 2.12 x 10^18 0+/cm^2 at an energy of 150 keV/atom.
Date: December 1982
Creator: Hamdi, Aboud Helal
Partner: UNT Libraries

Micromachined VLSI 3D electronics. Final report for period September 1, 2000 - March 31, 2001

Description: The phase I program investigated the construction of electronic interconnections through the thickness of a silicon wafer. The novel aspects of the technology are that the length-to-width ratio of the channels is as high as 100:1, so that the minimum amount of real estate is used for contact area. Constructing a large array of these through-wafer interconnections will enable two circuit die to be coupled on opposite sides of a silicon circuit board providing high speed connection between the two.
Date: March 31, 2001
Creator: Beetz, C.P.; Steinbeck, J. & Hsueh, K.L.
Partner: UNT Libraries Government Documents Department

Variability-aware low-power techniques for nanoscale mixed-signal circuits.

Description: New circuit design techniques that accommodate lower supply voltages necessary for portable systems need to be integrated into the semiconductor intellectual property (IP) core. Systems that once worked at 3.3 V or 2.5 V now need to work at 1.8 V or lower, without causing any performance degradation. Also, the fluctuation of device characteristics caused by process variation in nanometer technologies is seen as design yield loss. The numerous parasitic effects induced by layouts, especially for high-performance and high-speed circuits, pose a problem for IC design. Lack of exact layout information during circuit sizing leads to long design iterations involving time-consuming runs of complex tools. There is a strong need for low-power, high-performance, parasitic-aware and process-variation-tolerant circuit design. This dissertation proposes methodologies and techniques to achieve variability, power, performance, and parasitic-aware circuit designs. Three approaches are proposed: the single iteration automatic approach, the hybrid Monte Carlo and design of experiments (DOE) approach, and the corner-based approach. Widely used mixed-signal circuits such as analog-to-digital converter (ADC), voltage controlled oscillator (VCO), voltage level converter and active pixel sensor (APS) have been designed at nanoscale complementary metal oxide semiconductor (CMOS) and subjected to the proposed methodologies. The effectiveness of the proposed methodologies has been demonstrated through exhaustive simulations. Apart from these methodologies, the application of dual-oxide and dual-threshold techniques at circuit level in order to minimize power and leakage is also explored.
Date: May 2009
Creator: Ghai, Dhruva V.
Partner: UNT Libraries

HMC-to-flatpack attachment

Description: A method has been developed for attaching a completed hybrid microcircuit to a flatpack which can then be hermetically sealed. Ablefilm 517B and Epo-Tek H77 epoxies, in conjunction with an abraded flatpack and applied pressure during cure, were shown to provide HMC-to-flatpack bonds which meet all environmental and processing requirements of hybrid microcircuits in two recent programs.
Date: April 1, 1978
Creator: Zawicki, L.R.
Partner: UNT Libraries Government Documents Department