Description: The fastest commercially available 16-bit ADC can only perform around 200 mega-samples per second (200 MS/s). Connecting ADC chips together in eight different time domains increases the quantity of samples taken by a factor of eight. This method of interleaving requires that the input signal being sampled is split into eight identical signals and arrives at each ADC chip at the same point in time. The splitting of the input signal is performed in the analog front end containing a wideband filter that impedance matches the input signal to the ADC chips. Each ADC uses a clock to tell it when to perform a conversion. Using eight unique clocks spaced in 45-degree increments is the method used to time shift when each ADC chip performs its conversion. Given that this control clock is a fixed frequency, the clock phase shifting is accomplished by tightly controlling the distance that the clock must travel, resulting in a time delay. The interleaved ADC chips will now generate digital data in eight different time domains. These data are processed inside a field-programmable gate array (FPGA) to move the data back into a single time domain and store it into memory. The FPGA also contains a Nios II processor that provides system control and data retrieval via Ethernet.
Date: May 1, 2012
Item Type: Refine your search to only Article
Partner: UNT Libraries Government Documents Department