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FPIX core architecture and the preFPIX2 chip: Architecture and simulation

Description: preFPIX2 is a developmental step in the evolution of the final BTeV pixel architecture. It is a smaller version of a fully functional FPIX Core. It is a necessary step between FPIX1 and FPIX2 mostly for monetary reasons. Both FPIX1 and FPIX2 must be bump bonded to 18 x 160 arrays of ATLAS pixel detectors. Therefore, since each pixel is 50 {micro}m by 400 {micro}m, each FPIX chip cannot possibly be smaller than 7.2 mm by 8 mm. Since such a large chip is expensive, the collaborators are only being conservative by producing smaller versions of full FPIX chips when testing different ideas. Most importantly, preFPIX2 continues a progression towards smaller and smaller device geometries. FPIX0 was developed using Hewlett-Packard's 0.8 {micro}m CMOS process. FPIX1 was developed using Hewlett-Packard's 0.5 {micro}m CMOS process. FPIX2 will be developed in IBM's 0.25 {micro}m process or TSMC's 0.25 {micro}m process or in both processes. The major objectives of the development of preFPIX2 are to test the ability to successfully develop deep submicron IC chips and to test the capabilities of both the TSMC and IBM processes. The goal of reducing the process geometry is to take advantage of the higher and higher radiation tolerances they provide. To further the goal of high radiation tolerance, FPIX2 will be developed using radiation tolerant design techniques, in particular, enclosed transistors. preFPIX2 is the first functional chip developed at Fermilab to use such techniques. Finally, preFPIX2 has been developed to test a number of algorithmic modifications to the original read-out control developed in FPIX1. The FPIX1 readout architecture, also called the Command Driven Architecture, has been highly successful in all tests. However, it was decided that it could be improved substantially and simplified dramatically without changing it fundamentally. The purpose of this paper is to describe in ...
Date: July 1, 2000
Creator: Hoff, Jim; Mekkaoui, Abder & /Fermilab
Partner: UNT Libraries Government Documents Department

A new concept of vertically integrated pattern recognition associative memory

Description: Hardware-based pattern recognition for fast triggering on particle tracks has been successfully used in high-energy physics experiments for some time. The CDF Silicon Vertex Trigger (SVT) at the Fermilab Tevatron is an excellent example. The method used there, developed in the 1990's, is based on algorithms that use a massively parallel associative memory architecture to identify patterns efficiently at high speed. However, due to much higher occupancy and event rates at the LHC, and the fact that the LHC detectors have a much larger number of channels in their tracking detectors, there is an enormous challenge in implementing fast pattern recognition for a track trigger, requiring about three orders of magnitude more associative memory patterns than what was used in the original CDF SVT. Scaling of current technologies is unlikely to satisfy the scientific needs of the future, and investments in transformational new technologies need to be made. In this paper, we will discuss a new concept of using the emerging 3D vertical integration technology to significantly advance the state-of-the-art for fast pattern recognition within and outside HEP. A generic R and D proposal based on this new concept, with a few institutions involved, has recently been submitted to DOE with the goal to design and perform the ASIC engineering necessary to realize a prototype device. The progress of this R and D project will be reported in the future. Here we will only focus on the concept of this new approach.
Date: November 1, 2011
Creator: Liu, Ted; Hoff, Jim; Deptuch, Grzegorz; Yarema, Ray & /Fermilab
Partner: UNT Libraries Government Documents Department

Proposal for the development of 3D Vertically Integrated Pattern Recognition Associative Memory (VIPRAM)

Description: Future particle physics experiments looking for rare processes will have no choice but to address the demanding challenges of fast pattern recognition in triggering as detector hit density becomes significantly higher due to the high luminosity required to produce the rare process. The authors propose to develop a 3D Vertically Integrated Pattern Recognition Associative Memory (VIPRAM) chip for HEP applications, to advance the state-of-the-art for pattern recognition and track reconstruction for fast triggering.
Date: October 1, 2010
Creator: Deptuch, Gregory; Hoff, Jim; Kwan, Simon; Lipton, Ron; Liu, Ted; Ramberg, Erik et al.
Partner: UNT Libraries Government Documents Department

3D design activities at Fermilab: Opportunities for physics

Description: Fermilab began exploring the technologies for vertically integrated circuits (also commonly known as 3D circuits) in 2006. These technologies include through silicon vias (TSV), circuit thinning, and bonding techniques to replace conventional bump bonds. Since then, the interest within the High Energy Physics community has grown considerably. This paper will present an overview of the activities at Fermilab over the last 3 years which have helped spark this interest.
Date: January 1, 2009
Creator: Yarema, Raymond; Deptuch, Grezgorz; Hoff, Jim; Shenai, Alpana; Trimpl, Marcel; Zimmerman, Tom et al.
Partner: UNT Libraries Government Documents Department

Fermilab silicon strip readout chip for BTev

Description: A chip has been developed for reading out the silicon strip detectors in the new BTeV colliding beam experiment at Fermilab. The chip has been designed in a 0.25 {micro}m CMOS technology for high radiation tolerance. Numerous programmable features have been added to the chip, such as setup for operation at different beam crossing intervals. A full size chip has been fabricated and successfully tested. The design philosophy, circuit features, and test results are presented in this paper.
Date: May 1, 2005
Creator: Yarema, Raymond; Hoff, Jim; Mekkaoui, Abderrezak; Manghisoni, Massimo; Re, Valerio; Angeleri, Valentina et al.
Partner: UNT Libraries Government Documents Department