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Fabric-based systems: model, tools, applications.

Description: A Fabric Based System is a parameterized cellular architecture in which an array of computing cells communicates with an embedded processor through a global memory . This architecture is customizable to different classes of applications by funtional unit, interconnect, and memory parameters, and can be instantiated efficiently on platform FPGAs . In previous work, we have demonstrated the advantage of reconfigurable fabrics for image and signal processing applications . Recently, we have build a Fabric Generator, a Java-based toolset that greatly accelerates construction of the fabrics presented in. A module-generation library is used to define, instantiate, and interconnect cells' datapaths . FG generates customized sequencers for individual cells or collections of cells . We describe the Fabric-Based System model, the FG toolset, and concrete realizations offabric architectures generated by FG on the Altera Excalibur ARM that can deliver 4.5 GigaMACs/s (8/16 bit data, Multiply-Accumulate) .
Date: January 1, 2003
Creator: Wolinski, C. (Christophe); Gokhale, M. (Maya) & McCabe, K. P. (Kevin P.)
Partner: UNT Libraries Government Documents Department

A preliminary study of molecular dynamics on reconfigurable computers

Description: In this paper we investigate the performance of platform FPGAs on a compute-intensive, floating-point-intensive supercomputing application, Molecular Dynamics (MD). MD is a popular simulation technique to track interacting particles through time by integrating their equations of motion. One part of the MD algorithm was implemented using the Fabric Generator (FG)[l I ] and mapped onto several reconfigurable logic arrays. FG is a Java-based toolset that greatly accelerates construction of the fabrics from an abstract technology independent representation. Our experiments used technology-independent IEEE 32-bit floating point operators so that the design could be easily re-targeted. Experiments were performed using both non-pipelined and pipelined floating point modules. We present results for the Altera Excalibur ARM System on a Programmable Chip (SoPC), the Altera Strath EPlS80, and the Xilinx Virtex-N Pro 2VP.50. The best results obtained were 5.69 GFlops at 8OMHz(Altera Strath EPlS80), and 4.47 GFlops at 82 MHz (Xilinx Virtex-II Pro 2VF50). Assuming a lOWpower budget, these results compare very favorably to a 4Gjlop/40Wprocessing/power rate for a modern Pentium, suggesting that reconfigurable logic can achieve high performance at low power on jloating-point-intensivea pplications.
Date: January 1, 2003
Creator: Wolinski, C. (Christophe); Trouw, F. R. (Frans R.) & Gokhale, M. (Maya)
Partner: UNT Libraries Government Documents Department

New polymorphous computing fabric.

Description: This paper introduces a new polymorphous computing Fabric well suited to DSP and Image Processing and describes its implementation on a Configurable System on a Chip (CSOC). The architecture is highly parameterized and enables customization of the synthesized Fabric to achieve high performance for a specific class of application. For this reason it can be considered to be a generic model for hardware accelerator synthesis from a high level specification. Another important innovation is the Fabric uses a global memory concept, which gives the host processor random access to all the variables and instructions on the Fabric. The Fabric supports different computing models including MIMD, SPMD and systolic flow and permits dynamic reconfiguration. We present a specific implementation of a bank of FIR filters on a Fabric composed of 52 cells on the Altera Excalibur ARM running at 33 MHz. The theoretical performance of this Fabric is 1.8 GMACh. For the FIR application we obtain 1.6 GMAC/s real performance. Some automatic tools have been developed like the tool to provide a host access utility and assembler.
Date: January 1, 2002
Creator: Wolinski, C. (Christophe); Gokhale, M. (Maya) & McCabe, K. P. (Kevin P.)
Partner: UNT Libraries Government Documents Department

Co-design of software and hardware to implement remote sensing algorithms

Description: Both for offline searches through large data archives and for onboard computation at the sensor head, there is a growing need for ever-more rapid processing of remote sensing data. For many algorithms of use in remote sensing, the bulk of the processing takes place in an 'inner loop' with a large number of simple operations. For these algorithms, dramatic speedups can often be obtained with specialized hardware. The difficulty and expense of digital design continues to limit applicability of this approach, but the development of new design tools is making this approach more feasible, and some notable successes have been reported. On the other hand, it is often the case that processing can also be accelerated by adopting a more sophisticated algorithm design. Unfortunately, a more sophisticated algorithm is much harder to implement in hardware, so these approaches are often at odds with each other. With careful planning, however, it is sometimes possible to combine software and hardware design in such a way that each complements the other, and the final implementation achieves speedup that would not have been possible with a hardware-only or a software-only solution. We will in particular discuss the co-design of software and hardware to achieve substantial speedup of algorithms for multispectral image segmentation and for endmember identification.
Date: January 1, 2001
Creator: Theiler, J. P. (James P.); Frigo, J. (Janette); Gokhale, M. (Maya) & Szymanski, J. J. (John J.)
Partner: UNT Libraries Government Documents Department

An intelligent, onboard signal processing payload concept

Description: Our approach to onboard processing will enable a quicker return and improved quality of processed data from small, remote-sensing satellites. We describe an intelligent payload concept which processes RF lightning signal data onboard the spacecraft in a power-aware manner. Presently, onboard processing is severely curtailed due to the conventional management of limited resources and power-unaware payload designs. Delays of days to weeks are commonly experienced before raw data is received, processed into a human-usable format, and finally transmitted to the end-user. We enable this resource-critical technology of onboard processing through the concept of Algorithm Power Modulation (APM). APM is a decision process used to execute a specific software algorithm, from a suite of possible algorithms, to make the best use of the available power. The suite of software algorithms chosen for our application is intended to reduce the probability of false alarms through postprocessing. Each algorithm however also has a cost in energy usage. A heuristic decision tree procedure is used which selects an algorithm based on the available power, time allocated, algorithm priority, and algorithm performance. We demonstrate our approach to power-aware onboard processing through a preliminary software simulation.
Date: January 1, 2003
Creator: Shriver, P. M. (Patrick M.); Harikumar, J. (Jayashree); Briles, S. C. (Scott C.) & Gokhale, M. (Maya)
Partner: UNT Libraries Government Documents Department

Intelligent, onboard signal processing payload concept, addendum :

Description: This document addresses two issues in the original paper entitled 'An Intelligent, Onboard Signal Processing Payload Concept' submitted to the SPIE AeroSense 2003 C0nference.l Since the original paper submission, and prior to the scheduled presentation, a correction has been made to one of the figures in the original paper and an update has been performed to the software simulation of the payload concept. The figure, referred to as Figure 8. Simulation Results in the original paper, contains an error in the voltage versus the capacity drained chart. This chart does not correctly display the voltage changes experienced by the battery module due to the varying discharge rates. This error is an artifact of the procedure used to graph the data. Additionally, the original version of the Simulation related the algorithm execution rate to the lightning event rate regardless of the number of events in the ring buffer. This feature was mentioned in section 5. Simulation Results of the original paper. A correction was also made to the size of the ring buffer. Incorrect information was provided to the authors that placed the number of possible events at 18,310. Corrected information has since been obtained that specifies the ring buffer can typically hold only 1,000 events. This has a significant impact on the APM process and the number of events lost when the size of the ring buffer is exceeded. Also, upon further analysis, it was realized that the simulation contained an error in the recording of the number of events in the ring buffer. The faster algorithms, LMS and ML, should have been able to process all events during the simulation time interval, but the initial results did not reflect this characteristic. The updated version of the simulation appropriately handles the number of algorithm executions and recording of events in ...
Date: January 1, 2003
Creator: Shriver, P. M. (Patrick M.); Harikumar, J. (Jayashree); Briles, S. C. (Scott C.) & Gokhale, M. (Maya)
Partner: UNT Libraries Government Documents Department

Power-aware improvement in signal detection.

Description: Improvements in signal detection characteristics for a remote-sensing instrument can be achieved at the expense of computational effort and the power associated with that effort. DSP used in remote sensing scenarios usually involves the detection of a signal and the estimation of parameters as sociated with that signal . Fortunately, the algorithms used for parameter estimation are the same algorithms which, through postprocessing decision making, decrease the false alarm rate . This post processing allows for the reduction in the false alarm rate as seen at the end product of the instrument . The level of false alarm reduction must be balanced against the amount of additional power that is needed to produce this level . This paper will present quantitative results that demonstrate this tradeoff for a specific application . This paper focuses on the detection of transient radio frequency (RF) events (e.g., lighting) as observed from the FORTE satellite . However the methodology presented for power-aware improvement in signal detection is general enough to be applied to most remote-sensing scenarios . A suite of algorithms, which vary widely in their precision of estimated parameters, is presented in the paper . Equally wide in variation is the amount of power required by each of the algorithms. Power requirements of the algorithms were obtained by actual physical measurement for a mimic of a RAD750 processor . Algorithm performance was determined via Monte Carlo testing . Using that same Monte Carlo testing post-pro ce ssing, thresholds for each of the algorithms were developed for the reduction of the false alarm rate. A quantitative display of how each of the algorithms decreases the false alarm rate over the front-end analog detection is displayed versus the power required.
Date: January 1, 2003
Creator: Briles, S. D. (Scott D.); Shriver, P. M. (Patrick M.); Gokhale, M. (Maya) & Harikumar, J. (Jayashree)
Partner: UNT Libraries Government Documents Department

PARAMETERIZED K-MEANS CLUSTERING FOR RAPID HARDWARE DEVELOPMENT TO ACCELERATE ANALYSIS OF SATELLITE DATA

Description: Reconfigurable hardware has successfully been used to obtain speed-up in the implementation of image processing algorithms over purely software based implementations. At HPEC 2000 111, we described research we have done in applying reconfigurable hardware to satellite image data for remote sensing applications. We presented an FPGA implementation of K-means clustering that exhibited two orders of magnitude speedup over a software implementation.
Date: January 1, 2001
Creator: Leeser, M. (Miriam),; Belanov, P. (Pavle); Estlick, M. (Michael); Gokhale, M. (Maya); Szymanski, J. J. (John J.) & Theiler, J. P. (James P.)
Partner: UNT Libraries Government Documents Department

Weighted order statistic classifiers with large rank-order margin.

Description: We describe how Stack Filters and Weighted Order Statistic function classes can be used for classification problems. This leads to a new design criteria for linear classifiers when inputs are binary-valued and weights are positive . We present a rank-based measure of margin that can be directly optimized as a standard linear program and investigate its effect on generalization error with experiment. Our approach can robustly combine large numbers of base hypothesis and easily implement known priors through regularization.
Date: January 1, 2003
Creator: Porter, R. B. (Reid B.); Hush, D. R. (Donald R.); Theiler, J. P. (James P.) & Gokhale, M. (Maya)
Partner: UNT Libraries Government Documents Department