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in creator/contributor: "Estreich, D."  
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Latch-up and radiation integrated circuit--LURIC: a test chip for CMOS latch-up investigation

Description: A CMOS integrated circuit test chip (Latch-Up and Radiation Integrated Circuit--LURIC) designed for CMOS latch-up and radiation effects research is described. The purpose of LURIC is (a) to provide information on the physics of CMOS latch-up, (b) to study the layout dependence of CMOS latch-up, and (c) to provide special latch-up test structures for the development and verification of a latch-up model. Many devices and test patterns on LURIC are also well suited for radiation effects studies. L… more
Date: November 1, 1978
Creator: Estreich, D.B.
Item Type: Refine your search to only Report
Partner: UNT Libraries Government Documents Department
open access

Latch-up in CMOS integrated circuits

Description: An analysis is presented of latch-up in CMOS integrated circuits. A latch-up prediction algorithm has been developed and used to evaluate methods to control latch-up. Experimental verification of the algorithm is demonstrated.
Date: April 1, 1978
Creator: Estreich, D.B. & Dutton, R.W.
Item Type: Refine your search to only Article
Partner: UNT Libraries Government Documents Department
open access

Latch-up control in CMOS integrated circuits

Description: The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS-integrated circuit structures. Under normal bias, the parasitic SCR is in its blocking state but, if subjected to a large voltage spike or if exposed to an ionizing environment, triggering may occur. This may result in device burn-out or loss of state. The problem has been extensively studied for space and weapons applications. Prevention of latch-up has been achieved in conservative design… more
Date: July 13, 1979
Creator: Ochoa, A.; Dawes, W.; Estreich, D. & Packard, H.
Item Type: Refine your search to only Article
Partner: UNT Libraries Government Documents Department
open access

Latch-up control in CMOS integrated circuits

Description: The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS structures. Under normal bias, the parasitic SCR is in its blocking state, but if subjected to a high-voltage spike or if exposed to an ionizing environment, triggering may occur. Prevention of latch-up has been achieved by lifetime control methods such as gold doping or neutron irradiation and by modifying the structure with buried layers. Smaller, next-generation CMOS designs will enhance… more
Date: January 1, 1979
Creator: Ochoa, A. Jr.; Estreich, D.B. & Dawes, W.R. Jr.
Item Type: Refine your search to only Article
Partner: UNT Libraries Government Documents Department
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