Description: This invention is comprised of a logical memory latch and cell, using logic and circuit modifications, provides SEU immunity without loss of speed. A single logic state is hardened against SEU using technology methods and the information concerning valid states is then based to simplify hardened circuit design.
Date: December 31, 1991
Creator: Corbett, W.T. & Weaver, H.T.
Item Type: Refine your search to only Patent
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