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High performance static latches with complete single event upset immunity

Description: This invention is comprised of a logical memory latch and cell, using logic and circuit modifications, provides SEU immunity without loss of speed. A single logic state is hardened against SEU using technology methods and the information concerning valid states is then based to simplify hardened circuit design.
Date: December 31, 1991
Creator: Corbett, W.T. & Weaver, H.T.
Partner: UNT Libraries Government Documents Department

Single event upset hardening techniques

Description: Integrated circuit logic states are maintained by virtue of specific transistor combinations being either on'' (conducting) or off'' (nonconducting). High energy ion strikes on the microcircuit generate photocurrents whose primary detrimental effect is to make off'' transistors appear on,'' confusing the logic state and leading to single event upset (SEU). Protection against these soft errors is accomplished using either technology or circuit techniques, actions that generally impact yield and performance relative to unhardened circuits. We describe, and using circuit simulations analyze, a technique for hardening latches which requires combinations of technology and circuit modifications, but which provides SEU immunity without loss of speed. Specifically, a single logic state is hardened against SEU using technology methods and the information concerning valid states is then used to simplify hardened circuit design. The technique emphasizes some basic hardening concepts, ideas for which will be reviewed. 3 refs., 2 figs.
Date: January 1, 1990
Creator: Weaver, H.T. & Corbett, W.T.
Partner: UNT Libraries Government Documents Department