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A Dual Dielectric Approach for Performance Aware Reduction of Gate Leakage in Combinational Circuits

Description: Design of systems in the low-end nanometer domain has introduced new dimensions in power consumption and dissipation in CMOS devices. With continued and aggressive scaling, using low thickness SiO2 for the transistor gates, gate leakage due to gate oxide direct tunneling current has emerged as the major component of leakage in the CMOS circuits. Therefore, providing a solution to the issue of gate oxide leakage has become one of the key concerns in achieving low power and high performance CMOS … more
Date: May 2006
Creator: Mukherjee, Valmiki
Item Type: Refine your search to only Thesis or Dissertation

Modeling and reduction of gate leakage during behavioral synthesis of nanoscale CMOS circuits.

Description: The major sources of power dissipation in a nanometer CMOS circuit are capacitive switching, short-circuit current, static leakage and gate oxide tunneling. However, with the aggressive scaling of technology the gate oxide direct tunneling current (gate leakage) is emerging as a prominent component of power dissipation. For sub-65 nm CMOS technology where the gate oxide (SiO2) thickness is very low, the direct tunneling current is the major form of tunneling. There are two contribution parts in… more
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Date: May 2006
Creator: Velagapudi, Ramakrishna
Item Type: Refine your search to only Thesis or Dissertation
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