Device fabrication and transport measurements of FinFETs built with 28Si SOI wafers towards donor qubits in silicon Page: 4 of 10
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layer was deposited to serve as a hard-mark for the fins. Electron beam lithography was
used to pattern the fin patterns along with the source/drain contact pads. The oxide
hard-mask and the SOI layer were then etched by reactive-ion etching to define the fins.
After the fin etch, a 3 nm thick sacrificial dry oxide was grown and removed in dilute
hydrofluoric acid to smoothen the SOI sidewall. Following sidewall smoothing, a 10 nm
thick dry oxide was grown, and 140 nm thick in-situ phosphorus-doped poly-crystalline
silicon was deposited as the gate material. A second electron beam lithography step
was carried out to define the gate patterns, and the poly-crystalline silicon gate was
patterned by another reactive-ion etching step. The wafers then received an arsenic
implant with a dose of 2 x 10'5/cm2 at 25 keV to create self-aligned degenerately doped
source/drain regions. Dopant activation was achieved by rapid thermal annealing. A
protective CVD oxide, tungsten metallization, and forming gas anneal completes the
basic device fabrication process. The thermal budget of the full device fabrication was
designed with consideration of self diffusion of 29Si from the 100 nm natural silicon layer
into the 28Si epitaxial layer. Control measurements by electron spin resonance at 9 K
showed linewidths of implanted 121Sb donors in the 28-SOI layers to be 0.2 G , while
the linewidth in natural siliocn is about 4 G , confirming the integrity of the isotope
enriched 28Si layer. From literature values of diffusivities , the expected self-diffusion
of 29Si under the thermal budgets used for device fabrication is only about 4 nm. A
SEM micrograph of a fabricated FinFET is shown in Fig. 2, prior to the final CVD oxide
deposition and metallization steps. A typical room temperature Id - Vd measurement
of the devices is shown in Fig. 3.
4. Transport Measurements
Electrical tranport properties at low temperature are critical for the application of
FinFETs as single spin readout devices. The device tested had the SOI layer pre-
implanted with 121Sb at 80 keV with a dose of 6 x 1011 cm-2 prior to all other fabrication
steps. The post-processing Sb profile peak is expected to be located at 35 nm from the
top of the SOI layer, with a peak concentration of 1017 cm-3 from TCAD simulations.
The fin width is 80 nm, gate-length 280 nm and height 200 nm. Approximately 130 donor
atoms reside in the fin under the gate for the given device dimensions. Low temperature
transport measurements were performed with the device mounted in a Helium-3 cryostat
with a base temperature of 320 mK. Low-frequency lock-in measurements at 100 Hz and
modulation amplitude of 500 pV applied to the drain was used to measure the device
conductance. The stability diagram of the device at the base temperature is shown
in Fig. 4, with several overlapping Coulomb blockade diamonds visible. The Coulomb
blockade structures might be caused by local defects at the oxide-silicon interface or
by surface roughness along the channel. It does not appear to be related to quantum
confinement under the entire gate length due to the relatively large dimensions of the
device. The overlapping diamonds in the stability diagram also indicates independent
charge trapping/blockade centers along the conduction path in the device . Fig. 5
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Lo, Cheuk Chi; Persaud, Arun; Dhuey, Scott; Olynick, Deirdre; Borondics, Ferenc; Martin, Michael C. et al. Device fabrication and transport measurements of FinFETs built with 28Si SOI wafers towards donor qubits in silicon, article, June 10, 2009; Berkeley, California. (digital.library.unt.edu/ark:/67531/metadc934232/m1/4/: accessed December 18, 2018), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.