Device fabrication and transport measurements of FinFETs built with 28Si SOI wafers towards donor qubits in silicon Page: 3 of 10
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silicon interfaces degrade the spin coherence time . Hence, donors should be placed
at least 15 nm away from the surface so that the donor electron interacts minimally
with the interface spin-noise sources , but at the same time kept shallow enough
to interact with the gate induced two-dimensional electron gas (2DEG) that is used
for spin-state readout detection in an EDMR experiment. In the case of FinFETs, the
oxide interface is present on both sides of the donor (Fig. la, b), hence we limit the
minimal width of the fins (w) to approximately 40 nm. Since the 2DEG is induced on
the side-walls of the fin in a FinFET, the top portion of the gate can be removed for
single-ion implantation without affecting the gating ability of the side gates (Fig. lc). In
additional, if separate contact leads are designed for the FinFet, the two side gates can
then be biased independently for optimal 2DEG-donor interaction with the split-gate
geometry (Fig. id).
The donor atom that would serve as the qubit has to be isolated from other
impurity atoms. However, in a conventional CMOS process, source and drain regions
are degenerately doped and some of the dopants might straggle during ion implantation
or diffuse into the channel, as is the case in recent single dopant transport measurements
in tri-gate FETs . Hence, the gate lengths (lg) for spin-state readout FinFETs are
designed to be > 250 nm as TCAD simultions indicate that the channel region will not be
accidentally doped by the source/drain dopants for devices with such long gate lengths,
given the processing conditions used. In addition, we use a different donor species in
the channel donor implant (antimony) and for the source/drain degenerate implants
(arsenic), and dopant species identification can be achieved through spectroscopic
transport measurements such as EDMR[18, 19].
Silicon-on-insulator (SOI) wafers are used for FinFET fabrication. However, for
spin qubits the presence of 29Si isotopes in natural silicon reduces the spin coherence
lifetime dramatically due to spectral diffusion , and nuclear spin free materials are
critical for spin qubit device development . The lack of commercially available
isotopically enriched 28Si SOI wafers led us to adopt a hybrid approach: 28Si is epitaxially
grown on a thin natural silicon SOI layer. When donors are implanted into the device,
we use sufficiently low implantation energies so that the donor electrons reside only
in the isotopically purified 28Si environment. After single-ion implantation is detected
electrically, the device has to be annealed at a high temperature for dopant activation.
Hence we use only tungsten for the metal layer of the device. The complete process flow
is described in detail in the next section.
3. Device fabrication
The starting substrates were silicon-on-insulator (SOI) wafers with natural isotope
compositions from Soitech. The top < 100 > silicon layer thickness was 100 nm and the
box thickness was 200 nm. 150 nm of isotopically enriched 28Si (>99.9%) was epitaxially
grown on the original SOI wafers, bringing the total top layer silicon thickness to 250
nm. A 100 nm thick low-temperature chemical-vapor deposited (CVD) silicon oxide
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Lo, Cheuk Chi; Persaud, Arun; Dhuey, Scott; Olynick, Deirdre; Borondics, Ferenc; Martin, Michael C. et al. Device fabrication and transport measurements of FinFETs built with 28Si SOI wafers towards donor qubits in silicon, article, June 10, 2009; Berkeley, California. (digital.library.unt.edu/ark:/67531/metadc934232/m1/3/: accessed February 19, 2019), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.