Commissioning of the Digital Transverse Bunch-by-Bunch Feedback System for the Tls. Page: 4 of 5

                                
mode, the feedback processor is operated in four parallel
channels of the ADC and the FIR filter. A dynamic range
of several mm is required to prevent saturation by the
perturbation at injection, or by a large distortion of closed
orbit. The 12-bit resolution ADC can fulfil the dynamic
range requirement without a correlator (notch) filter. The
bunch rate or RF frequency is 499.654 MHz and the
harmonic number is 200. The feedback processor and
ADCs are operated with a clock frequency of faR/4. The
fR was selected as the carrier frequency of the signal
from the BPM electrodes. According to this signal, the
frequency band of the beam motion covers from 1/2 faR to
3/2 fa. A FIR filter of up to 20 taps is supported by the
FPGA processor. Up to 32 sets of FIR filter coefficients
can be stored in the internal register of FPGA and are
selectable via a USB 2.0 interface or with an external
logic input. In the latter case, the switching speed is about
10 nsec. This function makes the system very flexible for
use in grow-damp experiments. Up to 256 historic Mega-
samples of ADC can be stored in the double-data rate
(DDR) memory in the feedback processor. Therefore, up
to 256 ms of data can be stored in the memory. The
latency time of the feedback processor is around 300
nsec. A good frequency response of the FIR filter can
easily be achieved using a two-turn delay (800 nsec) in
the transverse feedback loop. The frequency multiplier
supplies a DAC clock at the RF frequency with a cycle-
to-cycle jitter of 50 psec from the ADC clock. When jitter
is a problem, the external clock can replace the frequency
multiplier as clock source of DACs. The processor is
equipped with five DACs - four for the multiplexed FIR
filter output and one for multiplexed raw ADC data for
diagnostics and tuning. The latency of the multiplexed
FIR filter output can be controlled by adjusting the
internal delay. Each DAC has complementary outputs.
When several kicker electrodes are used for feedback, the
delay and polarity of the individual kicker must be tuned.
Such tuning is easily performed using these functions and
outputs.
This TLS feedback loop consists of one pick-up and
one kicker. The feedback FIR filter is linearly combined
with vertical and horizontal responses. Bunch oscillation
signals are multiplexed into four parallel channels in an
analog manner. Delay lines align the four consecutive
bunches in parallel sense. ADC with four parallel
channels and four FIR filters is used to process the
feedback signal. The differential output of the DACs
drives two power amplifiers. Figure 2 plots the typical
response of the FIR filter. A feedback FIR filter can be
designed in several ways. Time domain least square
fitting (TDLSF) [4] developed by Nakamura was applied
to the current configuration. The FIR filters also
compensate for the phase advance between the pick-up
and the kickers.

+ verris
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Fi-of,,o TI.,,
Figure 2. Measured transfer function of the prototype FIR
filter designed by time domain least square fitting
method.
A compact Flash (CF) card is used as a booting device
and stores configuration data of the feedback processor.
The USB 2.0 interface is provided to control the
processors and to transfer captured data. A device driver
of the feedback processor for the Linux kernel 2.4 is
developed and its most functions are controllable. The
device driver for Linux is available. Control software
from the NSRRC and Matlab are installed in a Linux PC
to provide a convenient environment for the interface of
the feedback processor. Matlab scripts control the
accelerator through the existing Matlab interface, the
feedback processor via the USB 2.0 interface, and
electronic instruments via the IEEE-488 interface. This
environment effectively supports various investigations.
COMMISSIONING RESULTS
New transverse feedback was commissioned in late
November. Figure 3 (a) shows numerous betatron
sidebands without feedback. These betatron sidebands are
fully suppressed by the feedback loop, as shown in Fig. 3
(b).
pAXY0 b.(300 mCpw..0c1D]90000  OPIAX.PJ,0500009000 p  O wX0100
.50   p(Y9,0S, d,3d0  F  50 50 .C d00WrA  -00*0050
- --
(a) Feedback loop open. (b) Feedback loop closed.
Figure 3. Transverse spectrum form harmonic 201 to 215
at the frequency of revolution frequency, fe. Strong
synchrotron lines are observed near the harmonics at the
revolution frequency as the longitudinal feedback was off.
Figure 4 shows the result of a grow/damp experiment
and its modal analysis [5, 6]. A damping time of less than
1 msec and an operating current of 300 mA were
achieved. Figure 5 shows the growth rate of mode 196.
The estimated growth rate for future 400 mA operation is
slightly less than 2 ms'I. The damping time including
feedback system is around -6 ms1 for the strongest mode,