Characterizing the Noise Performance of the KPiX ASIC Readout Chip

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AKPiX is a prototype front-end readout chip designed for the Silicon Detector Design Concept for the International Linear Collider (ILC). It is targeted at readout of the outer tracker and the silicon-tungsten calorimeter and is under consideration for the hadronic calorimeter and muon systems. This chip takes advantage of the ILC timing structure by implementing pulsed-power operation to reduce power and cooling requirements and buffered readout to minimize material. Successful implementation of this chip requires optimal noise performance, of which there are two measures. The first is the noise on the output signal, previously measured at 1500e{sup -}, which is ... continued below

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18 pages

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Carman, Jerome Kyrias & /SLAC, /Cabrillo Coll. November 7, 2007.

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AKPiX is a prototype front-end readout chip designed for the Silicon Detector Design Concept for the International Linear Collider (ILC). It is targeted at readout of the outer tracker and the silicon-tungsten calorimeter and is under consideration for the hadronic calorimeter and muon systems. This chip takes advantage of the ILC timing structure by implementing pulsed-power operation to reduce power and cooling requirements and buffered readout to minimize material. Successful implementation of this chip requires optimal noise performance, of which there are two measures. The first is the noise on the output signal, previously measured at 1500e{sup -}, which is much larger than the anticipated 500e{sup -}. The other is the noise on the trigger logic branch, which determines where thresholds must be set in order to eliminate noise hits, thus defining the smallest signals to which the chip can be sensitive. A test procedure has been developed to measure the noise in the trigger branch by scanning across the pedestal in trigger threshold and taking self-triggered data to measure the accept rate at each threshold. This technique measures the integral of the pedestal shape. Shifts in the pedestal mean from injection of known calibration charges are used to normalize the distribution in units of charge. The shape of the pedestal is fit well by a Gaussian, the width of which is determined to be 2480e{sup -}, far in excess of the expected noise. The variation of the noise as a function of several key parameters was studied, but no significant source has been clearly isolated. However, several problems have been identified that are being addressed or are under further investigation. Meanwhile, the techniques developed here will be critical in ultimately verifying the performance goals of the KPiX chip.

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18 pages

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  • Journal Name: Submitted to Journal of Undergraduate Studies

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  • Report No.: SLAC-TN-07-022
  • Grant Number: AC02-76SF00515
  • Office of Scientific & Technical Information Report Number: 919428
  • Archival Resource Key: ark:/67531/metadc886847

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Office of Scientific & Technical Information Technical Reports

Reports, articles and other documents harvested from the Office of Scientific and Technical Information.

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  • November 7, 2007

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  • Sept. 22, 2016, 2:13 a.m.

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  • Dec. 2, 2016, 9:12 p.m.

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Carman, Jerome Kyrias & /SLAC, /Cabrillo Coll. Characterizing the Noise Performance of the KPiX ASIC Readout Chip, article, November 7, 2007; [Menlo Park, California]. (digital.library.unt.edu/ark:/67531/metadc886847/: accessed April 27, 2018), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.