READOUT SYSTEM FOR ARRAYS OF FRISCH-RING CDZNTE DETECTORS. Page: 4 of 7
This article is part of the collection entitled: Office of Scientific & Technical Information Technical Reports and was provided to Digital Library by the UNT Libraries Government Documents Department.
The following text was automatically extracted from the image on this page using optical character recognition software:
Slot (6.5 mm deep)
Fig. 1. Detector module assembly.
With this approach, we assembled a detector module with
four crystals installed, three good ones and one that was
revealed to be faulty during the subsequent test. The good
ones are 4x4x12 mm long (small), 5x5x14 mm long (mid-
sized), and 6x6x14 mm long (large). The bad one is 5x5x14
III. DATA ACQUISITION SYSTEM
The design of the data-acquisition system (DAQ) considered
the possible portal hand-held application and used two
Application Specific Integrated Circutis (ASICs) developed at
BNL: a 16-channel low noise preamplifier ASIC for CZT
detector readout  and a peak detector/derandomizer (PDD)
ASIC -. The preamplifier ASIC has a continuous reset
system that enables it to self-adapt up to 150 nA leakage
current from the CZT detectors. Its input transistor and the
shaping circuit are optimized for the CZT detector application
so that the Equivalent Noise Charge (ENC) is only 93 e- with 2
pF input capacitor, 1 nA leakage current, and 1 fC input
charge. The PDD ASIC is a 32:1 multiplexer that uses analog
techniques (precision peak detectors and time-to-amplitude
converters) with arbitration logic to concentrate the data
before digitization. For signals arriving at any of its 32
channel inputs, the ASIC provides amplitude and timing
(occurrence time, rise time, or time-over-threshold) signals in
analog format and the channel number in digital format. Fig. 2
shows our system's structure based on these two ASICs.
Fig. 2. The structure of the data-acquisition system for the Frisch-ring
CZT detector array.
There are three PCB boards in this stacking system:
preamplifier board, PDD board, and controller board. The
detector modules reside on the top of the system.
Signals from each 16-channel detector module are amplified
by a preamplifier ASIC that has a programmable gain (33
mV/fC to 200 mV/fC) and peaking time (0.6 gs to 4.0 ps).
Output signals from two preamplifier ASICs are processed and
buffered in a PDD ASIC. Then, the amplitude and timing are
digitized by a 12-bit analog-to-digital converter (ADC).
Thereafter, all the digitized information is collected by a
FPGA and sent to a computer through a universal serial bus
(USB) controlled by a microcontroller . The computer has
DAQ software to control the system and process the data
Recently we designed and fabricated the detector module
and the preamplifier PCB board. To test these two boards, we
built a prototype system using the PDD test box  and the
MIOS system developed by BNL's Instrumentation Division.
This is a safe and satisfactory way to design the final compact
system, because the prototype system can help us to evaluate
our designs for the detector substrate and preamplifier, so
ensuring that they do not introduce extra electronic noise into
the system. Fig. 3 shows a photo of the whole system. Our
preamplifier boards are plugged into the PDD test box directly
(shown on the right in Fig. 3). The MIOS system (shown on
the left in Fig. 3), with a similar structure to our controller
board, digitizes the signals from PDD ASICs and sends the
data to computer.
Fig. 3. The DAQ system for the CZT detector array
IV. TEST RESULTS
We tested the system in the laboratory using both the pulse
generator and 137Cs gamma ray source. In this section, some
results from these four crystals are discussed.
The electronics noise was studied first when the prototype
system was built. To identify and understand the contributions
from different sources to the total noise, we measured the ENC
of the prototype system at different steps during system
integration steps: 1) with the preamplifier ASIC's input pins
lifted up; 2) with the preamplifier ASIC input pins soldered
onto the preamplifier board; 3) with the detector module
- S M PPO
Here’s what’s next.
This article can be searched. Note: Results may vary based on the legibility of text within the document.
Tools / Downloads
Get a copy of this page or view the extracted text.
Citing and Sharing
Basic information for referencing this web page. We also provide extended guidance on usage rights, references, copying or embedding.
Reference the current page of this Article.
CUI, Y.; BOLOTNIKOV, A.E.; CAMARDA, G.S.; DE GERONIMO, G.; O'CONNOR, P.; JAMES, R.B. et al. READOUT SYSTEM FOR ARRAYS OF FRISCH-RING CDZNTE DETECTORS., article, October 29, 2006; [Upton, New York]. (digital.library.unt.edu/ark:/67531/metadc882283/m1/4/: accessed January 18, 2019), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.