Fabrication of the GLAST Silicon Tracker Readout Electronics Page: 3 of 10
This report is part of the collection entitled: Office of Scientific & Technical Information Technical Reports and was provided to UNT Digital Library by the UNT Libraries Government Documents Department.
Extracted Text
The following text was automatically extracted from the image on this page using optical character recognition software:
3
IV. PWB
The PWB has 8 layers of traces and planes (z oz. Cu),
separated by 75 to 100 m of polyimide-glass dielectric
(Arlon 35N), except that the top two signal-trace layers are
separated by twice as much dielectric to reduce the
capacitance of the signal traces. Except for the raised edge,
the fabrication was standard technology [10], but with an
oddly shaped and rather crowded board. The minimum
conductor spacing is 100 m (4 mils), and the internal pads
are 500 m (20 mils) in diameter. Complete annular rings of
50 m (2-mils) minimum width were required on all internal
via connections. The outer layers were plated with 0.25 m
(10 -inch) of gold over 4 m (150 -inch) of nickel. The top
was protected by a standard green solder mask, but the back
side was covered with a bonded sheet of 50- m Kapton, for
electrical isolation of the 100 V SSD bias potential.
The long, narrow raised edge was formed by a technique
designed to maintain a straight edge and tight dimensional
tolerances. During fabrication, each panel contained 5 PWBs.
A second panel of the same size and made from the same
polyimide glass (but with no copper) was prepared with a
rectangular cutout over the location of each MCM. The two
panels were aligned by pins and bonded in a press, using an
acrylic adhesive. When the 5 MCMs were then routed out of
the bonded panels, all that remained on the MCMs from the
second panel was the narrow strip along the MCM edge. At
that point the edge was not yet rounded and the MCM was
slightly oversized.
The completed PWBs that passed all electrical tests and
coupon evaluations were sent to a machine shop to mill the
raised edge to the final height and required straightness and to
form a 1 mm radius. To ensure a smooth transition from the
radius to the straight edge, a custom cutting tool was made
that cut the radius and the flat edge simultaneously. At thessD
Right-Angle Interconnect
Amplifier ASICComposite Panel
C)
Thermal Boss
Connectorv,
SSD
Fig. 4. Cross section at the end of a tray, showing the
small gap in which the MCM is mounted between tray
and sidewall. The dimension line is from the SSD edge
to the midpoint between adjacent tower modules.other end of the 900 radius the tool was designed to leave a
discontinuity in slope of about 30 to allow for ample tolerance
in setting the depth of the cutter. The precision machining
was important in order to avoid cracking the flexible-circuit
traces when bending them around the edge and to ensure a
uniform edge for wire bonding between the SSDs and the
MCM.
In general the PWBs performed well, except for several
boards that formed short circuits between the 7th and 8th
layers. Those are the two layers with the bias potential
between them, and both layers include large planes of copper.
The short circuits formed at points well away from the plane
edges and well away from any vias. They were rare, never
occurring during preproduction testing, and were not found
until the completed MCMs were operated at 100 V in the
85 C burn-in chamber, usually in the first 24 hours of the 168-
hour burn-in. Despite a lot of effort in destructive physical
analysis, the root cause was never completely understood, but
the short circuits were shown to be associated with minute
impurities embedded in the prepreg.
The bias potential is operated at 100 V on all towers, which
is enough to ensure >99.5% detection efficiency for
minimum-ionizing particles passing through the SSDs at
normal incidence. However, since the supplies can be set as
high as 120 V, strictly speaking the dielectric thickness should
have been 200 m thick, as recommended by IPC 2221 [5] for
the 100 V to 150 V range. Instead, as part of an effort to
squeeze the electronics into the allocated space, the design
called for 100 m thick prepreg, formed from two layers,
which conforms to the IPC recommendations for the range
50 V to 100 V. The dielectric strength of the materials is far
more than sufficient at that thickness, and the design was
accepted by engineering review. But as we found out,
contaminants can cause failures even at 100 V or less.
Microscopic examinations done after the first short circuits
were encountered showed that in reality the first runs of
boards had only a single layer of prepreg between those
layers, which was squeezed down to 75 m thickness. We
then had the manufacturer change their process to conform to
the two layers specified in the drawings. Some shorts
nevertheless formed in boards from the revised process. By
that time in the project the entire original margin in space had
been used up elsewhere, and insufficient room and schedule-
time remained to remanufacture the boards with double the
dielectric thickness. Nevertheless, no failures were ever seen
after completion of the MCM burn-in or in the last % of the
burn-in period. The burn-in process was successful in
screening out the bad boards, albeit only after they had been
fully assembled. Long term failures cannot be ruled out, but
any single short circuit would result in the loss of only 1 out
of 2304 detector ladders, consequently with negligible
degradation of the instrument's scientific performance.
Upcoming Pages
Here’s what’s next.
Search Inside
This report can be searched. Note: Results may vary based on the legibility of text within the document.
Tools / Downloads
Get a copy of this page or view the extracted text.
Citing and Sharing
Basic information for referencing this web page. We also provide extended guidance on usage rights, references, copying or embedding.
Reference the current page of this Report.
Baldini, Luca; Brez, Alessandro; Himel, Thomas; Johnson, R. P.; Latronico, Luca; Minuti, Massimo et al. Fabrication of the GLAST Silicon Tracker Readout Electronics, report, March 3, 2006; [Menlo Park, California]. (https://digital.library.unt.edu/ark:/67531/metadc877938/m1/3/: accessed April 18, 2024), University of North Texas Libraries, UNT Digital Library, https://digital.library.unt.edu; crediting UNT Libraries Government Documents Department.