A fast continuous magnetic field measurement system based on digital signal processors Page: 2 of 4
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Fig. 1. Schematic diagram of the measurement system. The three major
blocks of the system signal manipulation (Signal Conditioning Board,
Programmable Gain Amplifier and Signal Processing Boards) are outlined in
separated boxes.
SCB accepts input signals from up to 10 sources (coils); in the
current version of the board only 5 inputs are activated. The
maximum input amplitude is 200 Vpp, which gives us the
capability to utilize large integral rotating coil probes, similar
to a 7 m long probe used in production measurements of the
LHC interaction region quadrupoles. Voltages from up to 5
coils can be bucked together. A current summing technique
has been used instead of the typical voltage summing method
for analog bucking, allowing simultaneous recording of raw
and bucked signals. To obtain small offsets and offset drifts,
low thermal EMF Coto relays (model 3602) have been used
for the control of the attenuation section. The SCB provides
attenuations of 1, 4, 10, 16, 20 for each signal except the
bucking one.
B. Programmable Gain Amplifiers Module
The PGA module is based on the commercially available
VMIVME-3419 board. It is a 32 channel signal conditioning
board with a range of manual gain selections: 1, 10, 100 and
1000; and full scale ranges from 10 mV to 1V. Three-
pole, active, filters are used on the input of every channel. In
our case the filters were selected for a cut-off frequency of 1
kHz. The major characteristics of the board are summarized
elsewhere [8].
The second part of the PGA block is an in-house made
Programmable Gain Control Mezzanine Card (PGCMC). It is
designed to provide the user wit the ability to change gains
automatically using a 12-bit data word from a standard TTL
digital I/O card. In our case, we use the VMIVME-25lOB
digital I/O card. This gives us the ability to change the
amplifier gains "on the fly" without powering down the VME
crate, changing the jumper settings for each desired channel.
This feature is important for software realization of automatic
gain control of the measurement system.
C. Signal Processing Boards Block
Two boards form the SPB block. The first one is a PentekA/D -D/A converter, model 6102 [9]. It is a high
performance, 8-channel converter for data acquisition and has
differential inputs to the A/D section featuring 16-bit
resolution, a maximum sampling frequency of 250 kHz and
16k samples FIFO per channel. This board is attached to a
second one, the Pentek model 4288 [10], which is the central
element of the system. This board contains the 40 MHz
AD2106 Super Harward Architecture Computer (SHARC)
DSP by Analog Devices. The SHARC processor delivers up
to 120 MFLOPS of computing power. Both boards
communicate through a proprietary high speed mezzanine bus,
Intel's Modular Interface eXtension (MIX) [11].
The conditioned signals are fed to the input of the A/D
converter and sampled at 40-50 kHz. When the "FIFO
HALF-FULL" is enabled, the digital buffer is transferred to
the local SRAM, accessible directly from the SHARC
processor. More details about data processing are presented in
section III, which describes the DSP firmware code.
D. Harmonic Trigger Module
The HTM board was developed and fabricated at Fermilab.
The main purpose of this board is to condition the signals
coming from the angular encoder which usually is directly
connected to the rotating probe shaft. It accepts the three
encoder signals, named 00, 900, and zero position or index
pulse, divides (by 1, 2, 4, 8 or 16) or multiplies (1, 2 or 4) a
selected encoder signal and provides it to the DSP for a proper
voltage-to-flux integration. In addition, divisions of 8 and 16
of the encoder pulses can be provided as an independent
trigger signal to a Digital Voltmeter (DVM) in the case that
such a device is used for additional monitoring.
Different features and checks were implemented into the
HTM board. It can enable and disable the trigger signals from
control sequences coming either on the VME bus or from the
front panel. An internal counter can be initialized to capture
the time difference between two index pulses and compare it
with the expected value. This information is provided to the
VME bus and can be used for monitoring purposes.
III. DSP CODE
The DSP firmware code was designed and written in-house.
The major task for this code is to transfer on-line the
information from A/D converter FIFO buffers into the
processor memory, integrate the input voltages to the fluxes
and transfer the flux values to the VME accessible memory
for reading by the control VME PPC computer. Special
treatment of the encoder pulses and the current reading
channel is performed.
A block diagram of the firmware code is shown in Fig.2.
The 16k word A/D FIFO is read in DMA mode into two 4k
word alternating input buffers. They are the major holders of
the data before signal processing. When enabled, the specific
A/D channel "FIFO HALF-FULL" interrupt triggers FIFO
readout. In standard operation, the first A/D channel contains
the digitally conditioned signal from the angular encoder of
the system (see Fig.1). When this signal is digitized, an
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Velev, G.V.; Carcagno, R.; DiMarco, J.; Kotelnikov, S.; Lamm, M.; Makulski, A. et al. A fast continuous magnetic field measurement system based on digital signal processors, article, September 1, 2005; Batavia, Illinois. (https://digital.library.unt.edu/ark:/67531/metadc877330/m1/2/: accessed April 18, 2024), University of North Texas Libraries, UNT Digital Library, https://digital.library.unt.edu; crediting UNT Libraries Government Documents Department.