Preliminary test results for the SVX4 Page: 4 of 49
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Preliminary Test Results for the SVX4
1 Introduction
There are presently two versions of the SVX4. Version 2 has on-chip bypassing and
Version 1 does not. The on-chip bypassing is a layer of transistors under the front-end
analog pipeline that acts as a bypassing capacitor for the voltage supply. Its size is about
a microfarad. We aggressively choose to test Version 2 because of this feature. The
feature is advantageous for hybrid design because it eliminates the need for an additional
passive component on the hybrid itself by placing it on the actual SVX4 die.
Also, the SVX4 was designed to operate in two modes: DO and CDF. One can set
which mode the chip will operate by placing a jumper in the proper position on the SVX4
chip carrier. In either mode, the chip can either use the operating parameters from the
shift register or the shadow register. Similarly, this is selected by placing a jumper on the
SVX4 chip carrier. This chip has this feature because it was unknown whether the new
design of the shadow register would be operable. The shadow register is also call the
SEU register or Single Event Upset register. An introduction into the functionality of the
chip and an explanation on the difference between DO and CDF mode can be found in
the SVX4 User's Manual [1].
2 Experimental Setup
Most of the results reported in this paper come from the Stimulus Test Stand. The test
stand is presently located at Wilson Hall on the fourteenth floor. Detailed descriptions of
the Stimulus Test Stand and the PATTO3 test stands can be found elsewhere [2,3].
3 Gain
In order to measure the gain, we wire-bonded four channels of the chip to four different
valued external capacitors. We then injected an external pulse into these channels using a
Hewlett-Packard 8112A Pulse Generator. The external pulse passes through a variable
attenuator to reduce its amplitude into the pV range (larger pulses will destroy the
amplifier input and channel). We can control the pulse height of the signal in two
independent methods: 1) varying the pulse height of the pulse generator (mV-V) and 2)
varying the attenuator (10-100 dB). The injected charge is then calculated by using
Q = Cext X Vpuiser x -20 logio (Vcap/ Vpuiser)
where Q is the total charge injected, Cext is the external capacitance bonded to the
channel, and -20 logio (Vcap/Vpuiser) is the attenuation factor [dB] with Vcap being the
actual voltage the external capacitor sees and Vpuiser being the output voltage of the
pulser.
After injecting the pulse into the channel, we measure the ADC output of the channel.
We then take the difference, A, between the ADC output of the injected signal and the
ADC output of the pedestal. The gain, G, is then calculated by
G-Q/A.DO Run II Silicon Group
DO Note 4250
Page 4
6/20/2005
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Christofek, L.; Hanagaki, K.; Rapidis, P. & Utes, M. Preliminary test results for the SVX4, report, June 1, 2005; Batavia, Illinois. (https://digital.library.unt.edu/ark:/67531/metadc873911/m1/4/: accessed April 23, 2024), University of North Texas Libraries, UNT Digital Library, https://digital.library.unt.edu; crediting UNT Libraries Government Documents Department.