The Hardware Implementation of the CERN SPS Ultrafast Feedback Processor Demonstrator Page: 1 of 4
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SLAC-PUB-15831
THE HARDWARE IMPLEMENTATION OF THE CERN SPS ULTRAFAST
FEEDBACK PROCESSOR DEMONSTRATOR*
J. E. Dusatko, J. M. Cesaratto, J. D. Fox, J. Olsen, C. H. Rivetta, SLAC, Menlo Park, California, USA
W. Ht6fle, CERN, Geneva, SwitzerlandAbstract
An ultrafast 4GSa/s transverse feedback processor has
been developed for proof-of-concept studies of feedback
control of e-cloud driven and transverse mode coupled
intra-bunch instabilities in the CERN SPS. This system
consists of a high-speed ADC on the front end and
equally fast DAC on the back end. All control and signal
processing is implemented in FPGA logic. This system is
capable of taking up to 16 sample slices across a single
SPS bunch and processing each slice individually within a
reconfigurable signal processor. This demonstrator
system is a rapidly developed prototype, consisting of
both commercial and custom-design components. It can
stabilize the motion of a single particle bunch using
closed loop feedback. The system can also run open loop
as a high-speed arbitrary waveform generator and
contains diagnostic features including a special ADC
snapshot capture memory. This paper describes the
overall system, the feedback processor and focuses on the
hardware architecture, design and implementation.
BACKGROUND
CERN is undertaking an intensity upgrade in their LHC
injector chain to allow full exploitation of the LHC at
high luminosity [1]. A side-effect of these upgrades is that
the planned factor of two increase in SPS beam intensity
leads to e-cloud and TMCI driven transverse intra-bunch
instabilities.
Much work has been done to understand this
phenomenon and develop possible control techniques
using simulation and measurements [2,3]. A progression
of this R&D effort has been the development of a
feedback control demonstrator system [4,5]. This
feedback demonstrator system provides a flexible means
for which to control and measure the feedback operation.
Using this system, we have been able to drive a single
bunch into instability and then use feedback to stabilize it.
OVERVIEW OF SYSTEM
The feedback demonstrator system is part of a larger
setup that includes an excitation system [6], as shown in
Fig. 1. The beam bunch motion is sensed by four
exponentially tapered striplines, whose outputs are
processed by an analog front end receiver. The receiver
sums the individual stripline plates in the horizontal and
vertical planes and takes the difference of the summed
plane pairs to obtain the bunch displacement signal. This
*Work supported by the U.S. Department of Energy under contract DE-
ACO2-76SF00515 and the US LHC Accelerator Research program
LARs)
j edu@ slac. stanfo rd. edusignal is then further low-pass filtered, amplified and
equalized. The last operation is performed to compensate
for distortions introduced by the pickup and cable plant.
The ADC has an input bandwidth of around 2GHz, which
is further limited to 800MHz by the analog front end
Bessel low-pass anti-aliasing filter.
Beam AFEP Amps
Pickup Receiver S A ck ira.
Te eedbackProcessor
SPS Inj
SPS RmiFreq 2GHz
200 ~ MUlt
The nalo corectin snali hn rcsedb h
Bac k End Kicker
Excitation
Systern
R F Power Amps
Figure 1: Overall Setup Block Diagram.
The feedback processor converts the analog bunch
position signal into the digital domain, performs an
algorithmic process on it and then converts it back to the
analog domain. The processor's bandwidth is 1.5GHz.
The analog correction signal is then processed by the
analog back end block which low-pass filters, amplifies,
splits and distributes it to four high power RF amplifiers
which drive the kicker structure, applying a corrective
field to the beam bunch. The DAC's output bandwidth is
limited to 1.5GHz, which is further reduced by the
200MHz bandwidth of the kicker.
The feedback processor output is combined using a
hybrid with the output of the excitation system. The latter
is essentially a programmable arbitrary waveform
generator, which allows us to generate a time-domain
drive signal along the same output path. This overall
setup allows us to perturb the beam into instability and
then correct it with feedback.
Three timing signals are received from the SPS low
level RF and timing systems: the 200MHz RF accelerator
reference clock (multiplied up to obtain the 2GHz sample
clock), the injection marker and the bunch revolution
maker. These signals allow us to synchronize sampling,
system timing and operation, and enables selection of
individual bunches within the SPS batch. Note that the
frequency multiplier can select any n*RF harmonic, up to
n=10 (2GHz); for our initial studies, we selected n=8
(1.6GHz) to simplify synchronization with the SPS.
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Dusatko, J. E.; Cesaratto, J. M.; Fox, J. D.; Olsen, J.; Rivetta, C. H. & Hofle, W. The Hardware Implementation of the CERN SPS Ultrafast Feedback Processor Demonstrator, article, November 8, 2013; United States. (https://digital.library.unt.edu/ark:/67531/metadc871432/m1/1/: accessed April 18, 2024), University of North Texas Libraries, UNT Digital Library, https://digital.library.unt.edu; crediting UNT Libraries Government Documents Department.