FAST ANALOGUE MULTIPLIERS WITH FIELD-EFFECT TRANSISTORS Page: 6 of 14
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(The extreme case would be with only one
transistor in the circuit when the
whole charging current flows to ground
through XF-3 producing no output.) The
output current flowing into the low
input impedance of current amplifier is
equal to the difference AI of channel
currents for x 1 0, y / 0. Bias
adjustment is provided for conductance
balancing of the two transistors, for
x = 0, y = y , zero output. In the
arrangement fown the channels are
driven symmetrically for maximum
linearity, and current driving of channels
can be used for temperature independence.
In a multiplier circuit the ratio
of maximum pulse length to the
multiplier solution time (i.e. to the
minimum pulse length) is determined
mainly by transformer design. Thus in
a multiplier which has to process longer
pulses, the solution time is solely
determined by transformer rise time.
A limiting factor in this respect is
XF-3 in the current driving mode. A
relatively high load resistance of
XF-3 (two channels in parallel R 500
ohms) requires high transformer
inductance to satisfy the required L/R
time constant. High resistance and
high inductance result both in an
increased rise time. Due to this, to
obtain the solution time as determined
by the field-effect transistor, a large
pulse length to solution time ratio.
requires voltage driving of XF-3. With
this, the output would have a temperature
dependence equal to that of the Channel
conductance. It is about -0.4 percent
/0 C over a relatively wide range and
should not be difficult to compensate.
The L/R and rise time requirements
of XF-2 are easier to satisfy as it is
terminated by the low input impedance
(m 20 ohms) of the current amplifier.
The component and performance data
of two multipliers for two ranges of
pulse length to solution time ratio
are given, for reasons of different
possible applications, obtainable
performance and design criteria. The
data (referring to Fig. 3) are given
in Table I and corresponding current
amplifiers in Fig. 4. Multiplier A
is moderately fast for 0.1-2 sec
pulse length and B a fast one for
20-100 nsec. For minimum residual
signals and aperiodic response, current
paths in the layout should be well
defined. There should be independent
returns for primary of XF-1 and XF-3,
a common ground for secondaries of
XF-1, XF-3, and a common ground for
secondary of XF-2 and current amplifier.
Capacitors from points 4, 6 to ground
are needed only in case B to balance
the stray capacitances of points 1, 3,
4, 6 for y yma , x = 0. Output of
multiplier B is shown in Fig. 5.
The field-effect transistors used
are Siliconix 2N2608, p-channel, with
Woo = 3-4 volts, 1/Go % 500 ohms,
RbCb = 15-25 nsec at Vgo = 1V. They
possess a high channel conductance-to-
gate voltage linearity. They also
have a high degree of channel symmetry
(possibly due to S-shaped planar struc-
ture), which is essential with this
method of charging current compensation.
The asymmetry 'of a field-effect
transistor can be measured in the fast
multiplier circuit (B) with points
2, 5 shorted to ground by observing
the residual signal for x = x;
y = 0 and reversing the channel leads.
It is shown that the conductance
and multiplication error due to finite
charging time of the field-effect
transistor decreases as exp (-t/T),
with time constant T equal to about
1/10 of the product of junction
capacitance and channel resistance.
This results in minimum solution time
of 10-20 nsec for typical devices,
depending on the accuracy required.
The simple method for compensation
of gate-channel junction charging .
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Radeka, V. FAST ANALOGUE MULTIPLIERS WITH FIELD-EFFECT TRANSISTORS, article, October 1, 1963; Upton, New York. (https://digital.library.unt.edu/ark:/67531/metadc867435/m1/6/: accessed May 26, 2019), University of North Texas Libraries, Digital Library, https://digital.library.unt.edu; crediting UNT Libraries Government Documents Department.