Critical Path-Based Thread Placement for NUMA Systems

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Multicore multiprocessors use a Non Uniform Memory Architecture (NUMA) to improve their scalability. However, NUMA introduces performance penalties due to remote memory accesses. Without efficiently managing data layout and thread mapping to cores, scientific applications, even if they are optimized for NUMA, may suffer performance loss. In this paper, we present algorithms and a runtime system that optimize the execution of OpenMP applications on NUMA architectures. By collecting information from hardware counters, the runtime system directs thread placement and reduces performance penalties by minimizing the critical path of OpenMP parallel regions. The runtime system uses a scalable algorithm that derives ... continued below

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Su, C Y; Li, D; Nikolopoulos, D S; Grove, M; Cameron, K & de Supinski, B R November 1, 2011.

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Multicore multiprocessors use a Non Uniform Memory Architecture (NUMA) to improve their scalability. However, NUMA introduces performance penalties due to remote memory accesses. Without efficiently managing data layout and thread mapping to cores, scientific applications, even if they are optimized for NUMA, may suffer performance loss. In this paper, we present algorithms and a runtime system that optimize the execution of OpenMP applications on NUMA architectures. By collecting information from hardware counters, the runtime system directs thread placement and reduces performance penalties by minimizing the critical path of OpenMP parallel regions. The runtime system uses a scalable algorithm that derives placement decisions with negligible overhead. We evaluate our algorithms and runtime system with four NPB applications implemented in OpenMP. On average the algorithms achieve between 8.13% and 25.68% performance improvement compared to the default Linux thread placement scheme. The algorithms miss the optimal thread placement in only 8.9% of the cases.

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PDF-file: 10 pages; size: 0.7 Mbytes

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  • Presented at: 2nd International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computing Systems (PMBS11), Seattle, WA, United States, Nov 13 - Nov 13, 2011

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  • Report No.: LLNL-CONF-510002
  • Grant Number: W-7405-ENG-48
  • Office of Scientific & Technical Information Report Number: 1035298
  • Archival Resource Key: ark:/67531/metadc843606

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Office of Scientific & Technical Information Technical Reports

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  • November 1, 2011

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  • May 19, 2016, 3:16 p.m.

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  • Nov. 23, 2016, 12:07 p.m.

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Su, C Y; Li, D; Nikolopoulos, D S; Grove, M; Cameron, K & de Supinski, B R. Critical Path-Based Thread Placement for NUMA Systems, article, November 1, 2011; Livermore, California. (digital.library.unt.edu/ark:/67531/metadc843606/: accessed October 15, 2018), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.