Evaluation of soft-core processors on a Xilinx Virtex-5 field programmable gate array. Page: 33 of 37
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A. 1.2 Utilization Results
The utilization results for the PPC440 are compared against the uB and Leon3 and are shown in
A-3. Note that these results are for both the cache and FPU enabled. Also note that the DDR2 is
shown within the utilization results.
FX70T Resource Utilization
* rB. LMB, FPU e'-abled
*MWB LMB,BRAM, FPUenabled
* MB LMB, SRAM, PU enabled. cache enabled
MB: DDR, LMB, cache enabled, FPU enabled
m Lecu-3 AHBRAM ,FPU enabled, cache enabled
* Leor3 SRAMA, FPU enabled, cache enabled
* [e n3. DDR. FPU enabled, cache enabled
* Leor3FT: FTAHBRAM, FT IU 1. FT FPU, FT cache
* Leor3FT: FT SRAM, FT IU 1, FT FPU, FT cache
[ Lecr3FT DDR, FT IU L FT FPU FT cache
PPC440: PLB BRAM. FPU enabled, rache enabled -02
* PPC440: SRAM, FPU enabled, cache enabled -02
PPCddC: DDR, FPU enabled, cache enabled -02
Figure A-3. PPC440 resource utilization comparison.
Figure A-3 shows that the PPC440 utilizes fewer resources than the Leon3 and uB, which is
expected since extra resources are not required to generate the hard-core PPC440, unlike the
soft-core processors that require extra resources. The PPC440 design using static random-access
memory (SRAM) with cache does not use block random-access memory (BRAM) to instantiate
the cache. The design may be utilizing LUT-RAM to build the cache. The DDR2, on the other
hand, does appear to use BRAM for the cache.
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Learn, Mark Walter. Evaluation of soft-core processors on a Xilinx Virtex-5 field programmable gate array., report, April 1, 2011; United States. (https://digital.library.unt.edu/ark:/67531/metadc836670/m1/33/: accessed May 23, 2019), University of North Texas Libraries, Digital Library, https://digital.library.unt.edu; crediting UNT Libraries Government Documents Department.