Evaluation of soft-core processors on a Xilinx Virtex-5 field programmable gate array. Page: 30 of 37
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The purpose of this report was to show the performance for each processor while running both a
Dhrystone application, which benchmarks the fixed-point operations of the processor, and the
Whetstone application, which benchmarks single-precision floating point operations. Both
processors demonstrated an increased performance when enabling the FPU and cache, which is
expected. With cache enabled, the processors both achieved about a 20x speed-up. On the other
hand, with the FPU enabled, the Leon3 performed much better than the uB, achieving a speed-up
of about 400x to 1000x. This is much faster than the uB, which only saw about a 40x speed-up.
Resource utilization for each processor was also included within this report. By not utilizing the
FPU and cache, the Leon3 and uB processors were very comparable on the amount of resources
used. The uB saw larger resource utilization when using the DDR2 MPMC. When enabling the
cache, the uB saw in increase in BRAM usage, which was expected. The Leon3, on the other
hand, saw a large increase in resource utilization once the FPU was enabled. This could partly
account for the large performance increase when running the Whetstone application.
Performance is usually required when running a processor, which means utilizing the FPU and
cache. With both these enabled, the Leon3 performed much better than the uB, but utilized
many more resources than that processor.
Overall, both processors have their own trade-offs when used. The Leon3 appears to perform
much faster than the uB when utilizing the FPU, but uses more resources than the uB. Also, the
Leon3 FPU provides the ability to use both single-precision and double-precision floating-point
operations whereas the uB FPU can only perform single-precision. Both processors, though,
performed similarly when using cache and both were comparable in resources with cache
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Learn, Mark Walter. Evaluation of soft-core processors on a Xilinx Virtex-5 field programmable gate array., report, April 1, 2011; United States. (https://digital.library.unt.edu/ark:/67531/metadc836670/m1/30/: accessed May 27, 2019), University of North Texas Libraries, Digital Library, https://digital.library.unt.edu; crediting UNT Libraries Government Documents Department.