Evaluation of soft-core processors on a Xilinx Virtex-5 field programmable gate array. Page: 29 of 37
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Leon3 FT Resource Utilization
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Leon3FT.AHBRAM, FPU enabled, cache enabled
Leon3FT:AHBRAM, FT IU 1, FPU enabled, cache enabled
* Leon3FT AHERAM. FT IU 1, FT FPU enabled, cache
Leon3FT AHBRAM. FT IU 1. FPU. FT Cache
Leon3FT AHBRAM. FT IU 1. FT FPU. FT CACHE
Leon3FT. FTAHBRAM, FPU, cache
Leon3FT:FT AHBRAM, FT IU1, FT FPU, FT CACHE
* Leon3: SRAM, FPU enabled, cache enabled
Leon3FT SRAM, FT FPU. FT Cache. FT IU 1
Leon3FT FT 5RAM. FPU. cache
* Leon3FT. FT SRAM, FT IU 1, FT FPU, FT cache
Leon3FT FTAHERAM, FT SRAM, FT cache, FT FPU, FT IU 1
Figure 12. Leon3FT resource utilization.
As seen in Figure 12, resource utilization increased slightly when FT components were enabled.
Regardless of which FT component is enabled, the resource utilization for LUTs increased by an
additional 10% of available chip resources whereas registers increased by an additional 5% of
available chip resources. Also, as seen in Figure 12, the BRAM usage decreases by 10% of
available chip resources once the FT portion is enabled when utilizing the on-chip memory or the
SRAM memory. It appears that enabling the FT portions of the Leon3 increases LUT utilization
by about 10% of available chip resources and decreases BRAM utilization by about 10% of
available chip resources.
Overall the Leon3FT does not show a large resource increase when enabling the FPU, which is
partly due to the fact that the FPU-lite is already enabled. Therefore, there is only a slight
increase in resources going from the FPU-lite to the high-performance FPU.
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Learn, Mark Walter. Evaluation of soft-core processors on a Xilinx Virtex-5 field programmable gate array., report, April 1, 2011; United States. (https://digital.library.unt.edu/ark:/67531/metadc836670/m1/29/: accessed May 20, 2019), University of North Texas Libraries, Digital Library, https://digital.library.unt.edu; crediting UNT Libraries Government Documents Department.