Evaluation of soft-core processors on a Xilinx Virtex-5 field programmable gate array. Page: 21 of 37
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algorithm. The provided Leon3FT netlist configures the processor with a memory management
unit (MMU) and the IU was protected using the 8-bit parity option.
The memory configuration for testing was configured differently for each test. The FT
AHBRAM was used for on-chip memory and was configured as 64 KB. Note that this memory
For testing external memory the 8-bit FT external memory controller was used for SRAM and is
cacheable. EDAC with pipelining was enabled on the FT memory controller. Though enabled
in the hardware configuration, EDAC could not be enabled through software due to the size of
the SRAM on the ML507 board. The size of the SRAM on the ML507 board is only 36 bits, 32
data bits and 4 check bits. EDACing on the FT memory controller requires 7 check bits.
The DDR2SPA external memory controller was used for the DDR2 memory and is also
All hardware configurations that were enabled or disabled during testing are highlighted in red
within Figure 4.
The frequency for each test was also adjusted to evaluate the performance of the processor.
Testing was conducted using frequencies of 50, 80, and 100 MHz.
These frequencies were chosen to closely match that of the uB frequencies. Since the Leon3FT
design is implemented on the ML507 board, the core is clocked from the 100 MHz on-board
clock. This clock connects to a DCM in the design, and the DCM output clocks the majority of
the Leon3FT logic. We can reduce the clock rate of the DCM, but cannot go below 32 MHz due
to the constraints of the Xilinx DCM on an FX70T part. The DCM on the FX70T part is also
capable of a maximum speed of 140 MHz, but the Leon design would not operate above 100
MHz. Modifications could have been made to utilize faster speeds, but the intent of this testing
was to utilize the processor as is without making modifications to the design code itself in order
to get a baseline case.
To test the performance of the soft-core processor, two benchmark applications were used. The
Dhrystone v2.1 application was used to test fixed-point performance while the Whetstone vi.2
application was used to test floating-point performance.
When building the executables for these applications, all code data was either placed in:
" On-chip memory using the FT AHBRAM with FT cache enabled or disabled,
" 8-bit FT external memory using SRAM with FT cache enabled or disabled, or
" External memory using DDR2-SDRAM with FT cache enabled or disabled.
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Learn, Mark Walter. Evaluation of soft-core processors on a Xilinx Virtex-5 field programmable gate array., report, April 1, 2011; United States. (https://digital.library.unt.edu/ark:/67531/metadc836670/m1/21/: accessed May 21, 2019), University of North Texas Libraries, Digital Library, https://digital.library.unt.edu; crediting UNT Libraries Government Documents Department.