Evaluation of soft-core processors on a Xilinx Virtex-5 field programmable gate array. Page: 20 of 37
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All code compiled used either the v8 compiler switch, which allows the use of multiply/divide
instructions, or the soft-float compiler switch to allow the support of floating point operations.
The soft-float compiler switch is used to disable generation of floating point instructions. When
the FPU is enabled, the soft-float compiler switch was not used.
The Leon3 utilizes the sparc-elf-gcc compiler.
3.2.2 Leon3FT Core
All hardware configurations for the Leon3FT were built using the GRLTB implementation tool
Version 220.127.116.11 provided by Gaisler. In order to synthesize the design, Synplify Pro Version
9.6.1 was used. For place and route, Xilinx ISE Version 10.1.03 was used. The common
configuration is represented by the block diagram shown in Figure 5.
Virtex-5 FX70T FPGA
I FT MUL/DIV
LEON3FT SPASRC Support
I V8 Unit
I AHB INTERFACE
UART Timer 1/0 Port
Figure 5. Leon3FT block diagram.
As shown in Figure 5, the hardware configuration for the Leon3FT was similar for each test
performed. Blocks that are not highlighted in red were always enabled during testing. To test
the effect on benchmark performance, the Leon3FT was configured with either an IEEE-754
high-performance FPU or a fixed cache size of 24 KB. When either of these components was
used, the FT capability was enabled. Since the Leon3FT netlist is provided by Gaisler, the cache
size is fixed at a 2x8 KB instruction cache with 32 bytes/line and a 2x4 KB data cache with
16 bytes/line. The replacement algorithm is also fixed with the least recently replaced (LRR)
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Learn, Mark Walter. Evaluation of soft-core processors on a Xilinx Virtex-5 field programmable gate array., report, April 1, 2011; United States. (https://digital.library.unt.edu/ark:/67531/metadc836670/m1/20/: accessed May 19, 2019), University of North Texas Libraries, Digital Library, https://digital.library.unt.edu; crediting UNT Libraries Government Documents Department.