Evaluation of soft-core processors on a Xilinx Virtex-5 field programmable gate array. Page: 16 of 37
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3. TEST SETUP
The following sections describe the test setup used for evaluating the soft-core processors. All
hardware and software configurations were kept as similar as possible to provide comparable
benchmark scores. The Xilinx ML507 development board was used for this study, which
contains a Virtex-5 FX70T FPGA.
The following sections describe the hardware and software setup used to evaluate the
performance of the uB.
All hardware configurations for the uB were built using the Xilinx Platform Studio (XPS)
Version 10.1.03. The hardware setup was performed using the Base System Builder (BSB). The
common configuration is represented by the block diagram shown in Figure 3.
Virtex-5 FX70T FPGA
64 RM LMB MICROBLAZE DEBUG Dbu
I 64 RMDbgI
ns cin 32K Data PL
I ~PLB .-I
I IruI I
UART Timer Controller
Figure 3. MicroBlaze block diagram.
As shown in Figure 3, the hardware configuration for the uB was similar for each test performed.
Blocks that are not highlighted in red were always enabled during testing. To test the effect on
benchmark performance, the uB was configured with either an IEEE-754 single-precision FPU,
64 KB of cache, or both the cache and FPU. Note that the uB has a configurable cache size for
both the instruction cache and the data cache. For this test the cache was configured as 32 KB
for the data cache and 32 KB for the instruction cache.
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Learn, Mark Walter. Evaluation of soft-core processors on a Xilinx Virtex-5 field programmable gate array., report, April 1, 2011; United States. (https://digital.library.unt.edu/ark:/67531/metadc836670/m1/16/: accessed May 26, 2019), University of North Texas Libraries, Digital Library, https://digital.library.unt.edu; crediting UNT Libraries Government Documents Department.