Evaluation of soft-core processors on a Xilinx Virtex-5 field programmable gate array. Page: 14 of 37
This report is part of the collection entitled: Office of Scientific & Technical Information Technical Reports and was provided to Digital Library by the UNT Libraries Government Documents Department.
The following text was automatically extracted from the image on this page using optical character recognition software:
2.2 Leon3 Soft-Core Processor
Two versions of the Leon3 soft-core processor were used in this study: the open-source
processor and the licensed processor. Both of these processors are described in the following
2.2.1 Open-Source Core
The open-source Leon3 soft-core processor is a 32-bit processor core conforming to the IEEE-
1754 (SPARC V8) architecture. The block diagram of the Leon3 is shown in Figure 2.
's-Pr,-t R=, Star F
IEEE-7S4 FPU -ra:e B01&Jl
Cao-Pmcessor Iteger pipeline Defug port . . Det xg support i
HW MULDIV "terru t " ntFDt cornrDller
LDca IRAM I-Carde DG-Cace LmCl; DRAM
ITLB SRMMU DTLE
AM BA A HB Maser :32-'t.
Figure 2. Leon3 core block diagram.
The Leon3 is customizable to generate a smaller or faster implementation. Note that Gaisler
provides a high-performance FPU (GRFPU) and a light FPU (GRFPU-Lite), which uses fewer
resources and has a lower performance than the GRFPU. The GRFPU-Lite is not pipelined and
executes one floating-point operation at a time. Both versions of the FPU support double-
precision floating point operations. The GRFPU was used for this study and only performed
single-precision floating point operations using the Whetstone benchmark.
2.2.2 Licensed Core
The licensed core is also referenced as the Leon3FT because it was designed to be fault-tolerant
(FT) within an Actel RTAX FPGA. The licensed Leon3 will be referenced as Leon3FT
throughout the remainder of this paper. The Leon3FT used within this evaluation was not
intended to be fault-tolerant in a Xilinx device, but to use as a prototype and develop with an
equivalent netlist on a reconfigurable platform rather than with the complications of developing
on an OTP platform. Further testing of the fault-tolerant aspects of the Leon3FT on a Xilinx
FPGA will be tested in upcoming radiation tests.
Here’s what’s next.
This report can be searched. Note: Results may vary based on the legibility of text within the document.
Tools / Downloads
Get a copy of this page or view the extracted text.
Citing and Sharing
Basic information for referencing this web page. We also provide extended guidance on usage rights, references, copying or embedding.
Reference the current page of this Report.
Learn, Mark Walter. Evaluation of soft-core processors on a Xilinx Virtex-5 field programmable gate array., report, April 1, 2011; United States. (https://digital.library.unt.edu/ark:/67531/metadc836670/m1/14/: accessed May 21, 2019), University of North Texas Libraries, Digital Library, https://digital.library.unt.edu; crediting UNT Libraries Government Documents Department.