Fighting Fire with Fire: Modeling the Datacenter-Scale Effects of Targeted Superlattice Thermal Management

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Local thermal hot-spots in microprocessors lead to worst case provisioning of global cooling resources, especially in large-scale systems. However, efficiency of cooling solutions degrade non-linearly with supply temperature, resulting in high power consumption and cost in cooling - 50 {approx} 100% of IT power. Recent advances in active cooling techniques have shown on-chip thermoelectric coolers (TECs) to be very efficient at selectively eliminating small hot-spots, where applying current to a superlattice film deposited between silicon and the heat spreader results in a Peltier effect that spreads the heat and lowers the temperature of the hot-spot significantly to improve chip reliability. ... continued below

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PDF-file: 13 pages; size: 3.3 Mbytes

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Biswas, S; Tiwari, M; Theogarajan, L; Sherwood, T P & Chong, F T November 11, 2010.

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Local thermal hot-spots in microprocessors lead to worst case provisioning of global cooling resources, especially in large-scale systems. However, efficiency of cooling solutions degrade non-linearly with supply temperature, resulting in high power consumption and cost in cooling - 50 {approx} 100% of IT power. Recent advances in active cooling techniques have shown on-chip thermoelectric coolers (TECs) to be very efficient at selectively eliminating small hot-spots, where applying current to a superlattice film deposited between silicon and the heat spreader results in a Peltier effect that spreads the heat and lowers the temperature of the hot-spot significantly to improve chip reliability. In this paper, we propose that hot-spot mitigation using thermoelectric coolers can be used as a power management mechanism to allow global coolers to be provisioned for a better worst case temperature leading to substantial savings in cooling power. In order to quantify the potential power savings from using TECs in data center servers, we present a detailed power model that integrates on-chip dynamic and leakage power sources, heat diffusion through the entire chip, TEC and global cooler efficiencies, and all their mutual interactions. Our multiscale analysis shows that, for a typical data center, TECs allow global coolers to operate at higher temperatures without degrading chip lifetime, and thus save {approx}27% cooling power on average while providing the same processor reliability as a data center running at 288K.

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PDF-file: 13 pages; size: 3.3 Mbytes

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  • Presented at: International Symposium on Computer Architecture, San Jose, CA, United States, Jun 04 - Jun 08, 2011

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  • Report No.: LLNL-CONF-474345
  • Grant Number: W-7405-ENG-48
  • Office of Scientific & Technical Information Report Number: 1018774
  • Archival Resource Key: ark:/67531/metadc835396

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  • November 11, 2010

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  • May 19, 2016, 3:16 p.m.

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  • Nov. 28, 2016, 3:31 p.m.

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Biswas, S; Tiwari, M; Theogarajan, L; Sherwood, T P & Chong, F T. Fighting Fire with Fire: Modeling the Datacenter-Scale Effects of Targeted Superlattice Thermal Management, article, November 11, 2010; Livermore, California. (digital.library.unt.edu/ark:/67531/metadc835396/: accessed August 20, 2017), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.