A bunch to bucket phase detector for the RHIC LLRF upgrade platform

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As part of the overall development effort for the RHIC LLRF Upgrade Platform [1,2,3], a generic four channel 16 bit Analog-to-Digital Converter (ADC) daughter module was developed to provide high speed, wide dynamic range digitizing and processing of signals from DC to several hundred megahertz. The first operational use of this card was to implement the bunch to bucket phase detector for the RHIC LLRF beam control feedback loops. This paper will describe the design and performance features of this daughter module as a bunch to bucket phase detector, and also provide an overview of its place within the overall ... continued below

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Smith, K.S.; Harvey, M.; Hayes, T.; Narayan, G.; Polizzo, S. & Severino, F. March 28, 2011.

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As part of the overall development effort for the RHIC LLRF Upgrade Platform [1,2,3], a generic four channel 16 bit Analog-to-Digital Converter (ADC) daughter module was developed to provide high speed, wide dynamic range digitizing and processing of signals from DC to several hundred megahertz. The first operational use of this card was to implement the bunch to bucket phase detector for the RHIC LLRF beam control feedback loops. This paper will describe the design and performance features of this daughter module as a bunch to bucket phase detector, and also provide an overview of its place within the overall LLRF platform architecture as a high performance digitizer and signal processing module suitable to a variety of applications. In modern digital control and signal processing systems, ADCs provide the interface between the analog and digital signal domains. Once digitized, signals are then typically processed using algorithms implemented in field programmable gate array (FPGA) logic, general purpose processors (GPPs), digital signal processors (DSPs) or a combination of these. For the recently developed and commissioned RHIC LLRF Upgrade Platform, we've developed a four channel ADC daughter module based on the Linear Technology LTC2209 16 bit, 160 MSPS ADC and the Xilinx V5FX70T FPGA. The module is designed to be relatively generic in application, and with minimal analog filtering on board, is capable of processing signals from DC to 500 MHz or more. The module's first application was to implement the bunch to bucket phase detector (BTB-PD) for the RHIC LLRF system. The same module also provides DC digitizing of analog processed BPM signals used by the LLRF system for radial feedback.

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  • 2011 Particle Accelerator Conference (PAC'11); New York, NY; 20110328 through 20110401

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  • Report No.: BNL--94208-2011-CP
  • Grant Number: DE-AC02-98CH10886
  • Office of Scientific & Technical Information Report Number: 1016658
  • Archival Resource Key: ark:/67531/metadc834348

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Reports, articles and other documents harvested from the Office of Scientific and Technical Information.

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  • March 28, 2011

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  • May 19, 2016, 3:16 p.m.

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  • Aug. 29, 2016, 6:23 p.m.

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Smith, K.S.; Harvey, M.; Hayes, T.; Narayan, G.; Polizzo, S. & Severino, F. A bunch to bucket phase detector for the RHIC LLRF upgrade platform, article, March 28, 2011; United States. (digital.library.unt.edu/ark:/67531/metadc834348/: accessed December 15, 2017), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.