D0 Silicon Upgrade: CTF Front End Crate J2/J3 BAckplane Specification

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GENERAL PHYSICAL LAYOUT: (1) The backplane is comprised of 2 identical sections, the upper half designated J1, and the lower half designated j3; (2) For each section, there are a total of 16 slots, designated 1 through 16, from left to right; (3) Odd numbered slots are left handed (Connectors to the left of the card), these slots utilize inverse DIN connectors; (4) Even numbered slots are right handed (Connectors to the right of the card), these slots utilize standard DIN connectors; (5) There are 2 60 pin daisy-chain headers associated with each section, 3M part number 3597-6003; (6) The ... continued below

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4 pages

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Baert, Mark July 3, 1995.

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GENERAL PHYSICAL LAYOUT: (1) The backplane is comprised of 2 identical sections, the upper half designated J1, and the lower half designated j3; (2) For each section, there are a total of 16 slots, designated 1 through 16, from left to right; (3) Odd numbered slots are left handed (Connectors to the left of the card), these slots utilize inverse DIN connectors; (4) Even numbered slots are right handed (Connectors to the right of the card), these slots utilize standard DIN connectors; (5) There are 2 60 pin daisy-chain headers associated with each section, 3M part number 3597-6003; (6) The headers associated with the J2 (upper) section are designated J2CHAINR and J2CHAINL; (7) The headers associated with the J3 (lower) section are designated J3CHAINL and J3CHAINR; and (8) Mechanical layout presented in drawing number 3823.113-MD-330045. TRIGGER SIGNALS: (1) There are 21 trigger signal which originate from a given slot and are routed to the slot immediately to the left and 21 trigger signals which originate from a given slot and are routed to the slot immediately to the right; (2) There are 21 trigger signals which originate from the slot immediately to the left of a given slot and 21 trigger signals which originate from the slot immediately to the right a given slot; (3) The signal are designated TRIGjk-n, when j is the source slot, k is the destination slot, and n is the signal number; (4) These signals shall be implemented as 100 ohm microstip above ground plane; and (5) No terminations. DC POWER: (1) Each slot is supplied with DC power on the connector pins designated as VCC and GND; (2) VCC and GND originates at rear of the backplane via press-in power terminals, their locations are shown in drawing number 3823.113-MD-330045; (3) Power shall be bypassed at 2 locations with a 10uF tantalum capacitor in parallel with a .01uF 100V ceramic capacitor; and (4) The total ampacity supplied by each DIN connector is 3.6 amps.

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4 pages

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  • Report No.: FERMILAB-D0-EN-427
  • Grant Number: AC02-07CH11359
  • DOI: 10.2172/1033304 | External Link
  • Office of Scientific & Technical Information Report Number: 1033304
  • Archival Resource Key: ark:/67531/metadc834081

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  • July 3, 1995

Added to The UNT Digital Library

  • May 19, 2016, 3:16 p.m.

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  • Aug. 30, 2016, 4:07 p.m.

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Baert, Mark. D0 Silicon Upgrade: CTF Front End Crate J2/J3 BAckplane Specification, report, July 3, 1995; Batavia, Illinois. (digital.library.unt.edu/ark:/67531/metadc834081/: accessed December 10, 2018), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.