Energy-efficient specialization of functional units in a Coarse-Grained Reconfigurable Array

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Functional units provide the backbone of any spatial accelerator by providing the computing resources. The desire for having rich and expensive functional units is in tension with producing a regular and energy-efficient computing fabric. This paper explores the design trade-off between complex, universal functional units and simpler, limited functional units. We show that a modest amount of specialization reduces the area-delay-energy product of an optimized architecture to 0.86x a baseline architecture. Furthermore, we provide a design guideline that allows an architect to customize the contents of the computing fabric just by examining the profile of benchmarks within the application domains. ... continued below

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6 p. (0.1 MB)

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Van Essen, B; Panda, R; Wood, A; Ebeling, C & Hauck, S December 1, 2010.

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Functional units provide the backbone of any spatial accelerator by providing the computing resources. The desire for having rich and expensive functional units is in tension with producing a regular and energy-efficient computing fabric. This paper explores the design trade-off between complex, universal functional units and simpler, limited functional units. We show that a modest amount of specialization reduces the area-delay-energy product of an optimized architecture to 0.86x a baseline architecture. Furthermore, we provide a design guideline that allows an architect to customize the contents of the computing fabric just by examining the profile of benchmarks within the application domains. Functional units are the core of compute-intensive spatial accelerators. They perform the computation of interest with support from local storage and communication structures. Ideally, the functional units will provide rich functionality, supporting operations ranging from simple addition, to fused multiply-adds, to advanced transcendental functions and domain specific operations like add-compare-select. However, the total opportunity cost to support the more complex operations is a function of the cost of the hardware, the rate of occurrence of the operation in the application domain, and the inefficiency of emulating the operation with simpler operators. Examples of operations that are typically emulated in spatial accelerators are division and trigonometric functions, which can be solved using table-lookup based algorithms and the CORDIC algorithm. One reason to avoid having direct hardware support for complex operations in a tiled architecture like a Coarse-Grained Reconfigurable Array (CGRA) is that the expensive hardware will typically need to be replicated in some or all of the architecture's tiles. Tiled architecture are designed such that their tiles are either homogeneous or heterogeneous. Homogeneous architectures are simpler to design but heterogeneous architectures can be more efficient. Generally, CGRAs try to support a rich set of operations with the smallest possible set of hardware devices.

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6 p. (0.1 MB)

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PDF-file: 6 pages; size: 0.1 Mbytes

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  • Presented at: Nineteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, United States, Feb 27 - Mar 01, 2010

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  • Report No.: LLNL-CONF-463475
  • Grant Number: W-7405-ENG-48
  • Office of Scientific & Technical Information Report Number: 1017999
  • Archival Resource Key: ark:/67531/metadc833779

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  • December 1, 2010

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  • May 19, 2016, 3:16 p.m.

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  • April 13, 2017, 6:30 p.m.

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Van Essen, B; Panda, R; Wood, A; Ebeling, C & Hauck, S. Energy-efficient specialization of functional units in a Coarse-Grained Reconfigurable Array, article, December 1, 2010; Livermore, California. (digital.library.unt.edu/ark:/67531/metadc833779/: accessed October 21, 2017), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.