A new concept of vertically integrated pattern recognition associative memory Page: 4 of 10
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ONE PATTERN Ln er 1 La er 2 La er 3 LT er4
Cell 0 word word word word
Cell 1 FF FF FF FF
Cella 2F I FR i 1
C ll 1il 1 iiilT i i11
Fig. 2 - A Block Diagram of an Associative Memory Chip. The CAM Cells are shown as white (or yellow) boxes. The
Majority/Glue Logic is shown to the right as green semicircles.
Associative Memory is sometimes called PRAM, Pattern Recognition Associative Memory. The AM
method solves the combinatorial challenge inherent to the pattern recognition by exploiting massive
parallelism of associative memories that can compare tracking detector hits to a set of pre-calculated
patterns simultaneously. The found patterns or "fired roads" are then processed using fast FPGAs to
perform track fitting with full detector resolution using all combinations of the "hits of interest" from the
fired roads. Because each pattern or road is narrow enough, the usual helical fit can be replaced by a
simple linear calculation. The track fitting stage for each matched pattern is much simplified and can be
very fast .
3. Limitations of the 2D Approach
A critical figure of merit for an AM-based track reconstruction system is the number of predetermined
track patterns or roads that can be stored in the Associative Memory bank. Generally speaking, wider
roads using coarser resolution hits require less AM storage, but the number of AM roads satisfied by
random hits and the number of fits at the track fitting stage downstream increases quickly due to the high
detector occupancy. Also, the demand on the bandwidth would be higher because all the roads and hits
have to be transferred from the AM stage to the track fitting stage. If the roads are very narrow, due to
using finer resolution hits, the number of fake roads and fits are reduced, but the required total size of the
AM would increase dramatically. Therefore, the road width must be optimized. The required AM pattern
bank size will be different for different experiments and even different for the same experiment at
different luminosities. For CDF SVT upgrade, the AMchip03  was developed using 180 nm CMOS
technology and standard cell based approach. The AMchip03 has 5K patterns for six detector layers and
could work up to 50MHz. A new version, AMchip04, is currently being developed  using 65 nm for
the Atlas FTK project .
Future associative memory designs will require much more stored patterns per unit area at less power
per pattern and at greater speed. This is by no means a simple task, but the three elements - pattern
density, power and speed - are related to one another through geometry. Obviously, with smaller feature
sizes, more associative memory cells can be made in the same area. Furthermore, both power and speed
are directly proportional to load capacitance which is itself related to feature size. Therefore, the logical
approach to the requirements of future associative memory designs is to build them in smaller and smaller
feature sizes. However, this approach eventually fails both economically and technically. Economically,
each new process node is averaging a factor of 2.5 times in production cost over the preceding technology
node. Technically, the scaling of VLSI circuits reduces gate delay, but increases interconnect delay .
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Liu, Ted; Hoff, Jim; Deptuch, Grzegorz; Yarema, Ray & /Fermilab. A new concept of vertically integrated pattern recognition associative memory, article, November 1, 2011; Batavia, Illinois. (digital.library.unt.edu/ark:/67531/metadc831771/m1/4/: accessed February 17, 2019), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.