D0 Silicon Upgrade: Thermal Analysis of the D0 Double Sided Ladders

PDF Version Also Available for Download.

Description

A side view of the double sided ladder is shown in Figure 1. There are two types of double sided ladder; 6 chip and 9 chip. The 6 chip ladder has three SVX II chips mounted directly opposite the cooling channel and 3 chips mounted at the ladder end. The 9 chip ladder has 4 SVX II chips directly opposite the cooling channel and 5 chips at the ladder end. The power density is highest in the 6 chip ladder. All plots and calculations in this Engineering Note pertain to the 6 chip ladder with the understanding that the 9 ... continued below

Physical Description

7 pages

Creation Information

Ratzmann, Paul M. July 22, 1996.

Context

This report is part of the collection entitled: Office of Scientific & Technical Information Technical Reports and was provided by UNT Libraries Government Documents Department to Digital Library, a digital repository hosted by the UNT Libraries. More information about this report can be viewed below.

Who

People and organizations associated with either the creation of this report or its content.

Author

Publisher

Provided By

UNT Libraries Government Documents Department

Serving as both a federal and a state depository library, the UNT Libraries Government Documents Department maintains millions of items in a variety of formats. The department is a member of the FDLP Content Partnerships Program and an Affiliated Archive of the National Archives.

Contact Us

What

Descriptive information to help identify this report. Follow the links below to find similar items on the Digital Library.

Description

A side view of the double sided ladder is shown in Figure 1. There are two types of double sided ladder; 6 chip and 9 chip. The 6 chip ladder has three SVX II chips mounted directly opposite the cooling channel and 3 chips mounted at the ladder end. The 9 chip ladder has 4 SVX II chips directly opposite the cooling channel and 5 chips at the ladder end. The power density is highest in the 6 chip ladder. All plots and calculations in this Engineering Note pertain to the 6 chip ladder with the understanding that the 9 chip temperature profile is somewhat improved over the 6 chip due to the reduced power density in the row of chips opposite the cooling channel. The two dimensional finite difference technique used for these calculations is described in DOEN 447 and will not be described here. The assumed thermal conductivity of beryllium is 190 W/m-K, and that of silicon is 149 W/m-K. The SVX II power dissipation is assumed 0.400 W. There is no cable or hybrid component power dissipation in this set of simulations. The epoxy in the glue joints consists of 2 mils thickness of thermally conductive epoxy with 0.8 W/m-K conductivity and 1 mil thickness of 0.22 W/m-K unfilled epoxy. The assumed gas temperature outboard of the bulkhead is 15 C with a convection coefficient of 5 W/m{sup 2}-K. The cooling channel temperature is 0 C. The intention of this series of simulations is to determine the optimum thickness to achieve an acceptable silicon temperature during operation of the ladder. Once the operating temperature profile is known, the temperatures within the beryllium substrates are used as input for an ANSYS* calculation of the bow of the ladder during operation. A series of calculations have been performed over the last several months in order to consider the effect of thickness, chip power, gas temperature, etc. on the temperature profile. Only the final plots are shown here in runs 660, 661, and 662. In these three plots the conditions are identical except for the beryllium substrate thickness which is 0.3/0.3, 0.4/0.4, and 0.5/0.3 bottom/top beryllium thicknesses, which are in dimensions of mm.

Physical Description

7 pages

Language

Item Type

Identifier

Unique identifying numbers for this report in the Digital Library or other systems.

  • Report No.: FERMILAB-D0-EN-455
  • Grant Number: AC02-07CH11359
  • DOI: 10.2172/1033276 | External Link
  • Office of Scientific & Technical Information Report Number: 1033276
  • Archival Resource Key: ark:/67531/metadc831513

Collections

This report is part of the following collection of related materials.

Office of Scientific & Technical Information Technical Reports

Reports, articles and other documents harvested from the Office of Scientific and Technical Information.

Office of Scientific and Technical Information (OSTI) is the Department of Energy (DOE) office that collects, preserves, and disseminates DOE-sponsored research and development (R&D) results that are the outcomes of R&D projects or other funded activities at DOE labs and facilities nationwide and grantees at universities and other institutions.

What responsibilities do I have when using this report?

When

Dates and time periods associated with this report.

Creation Date

  • July 22, 1996

Added to The UNT Digital Library

  • May 19, 2016, 3:16 p.m.

Description Last Updated

  • Aug. 30, 2016, 4:10 p.m.

Usage Statistics

When was this report last used?

Yesterday: 0
Past 30 days: 0
Total Uses: 2

Interact With This Report

Here are some suggestions for what to do next.

Start Reading

PDF Version Also Available for Download.

Citations, Rights, Re-Use

Ratzmann, Paul M. D0 Silicon Upgrade: Thermal Analysis of the D0 Double Sided Ladders, report, July 22, 1996; Batavia, Illinois. (digital.library.unt.edu/ark:/67531/metadc831513/: accessed December 12, 2017), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.