Analysis of Photonic Networks for a Chip Multiprocessor Using Scientific Applications

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As multiprocessors scale to unprecedented numbers of cores in order to sustain performance growth, it is vital that these gains are not nullified by high energy consumption from inter-core communication. With recent advances in 3D Integration CMOS technology, the possibility for realizing hybrid photonic-electronic networks-on-chip warrants investigating real application traces on functionally comparable photonic and electronic network designs. We present a comparative analysis using both synthetic benchmarks as well as real applications, run through detailed cycle accurate models implemented under the OMNeT++ discrete event simulation environment. Results show that when utilizing standard process-to-processor mapping methods, this hybrid network can achieve ... continued below

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Kamil, Shoaib A.; Hendry, Gilbert; Biberman, Aleksandr; Chan, Johnnie; Lee, Benjamin G.; Mohiyuddin, Marghoob et al. January 31, 2009.

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As multiprocessors scale to unprecedented numbers of cores in order to sustain performance growth, it is vital that these gains are not nullified by high energy consumption from inter-core communication. With recent advances in 3D Integration CMOS technology, the possibility for realizing hybrid photonic-electronic networks-on-chip warrants investigating real application traces on functionally comparable photonic and electronic network designs. We present a comparative analysis using both synthetic benchmarks as well as real applications, run through detailed cycle accurate models implemented under the OMNeT++ discrete event simulation environment. Results show that when utilizing standard process-to-processor mapping methods, this hybrid network can achieve 75X improvement in energy efficiency for synthetic benchmarks and up to 37X improvement for real scientific applications, defined as network performance per energy spent, over an electronic mesh for large messages across a variety of communication patterns.

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  • The 3rd ACM/IEEE International Symposium on Networks-on-Chip, San Diego, CA, May 10-13, 2009

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  • Report No.: LBNL-4774E
  • Grant Number: DE-AC02-05CH11231
  • Office of Scientific & Technical Information Report Number: 1050630
  • Archival Resource Key: ark:/67531/metadc828228

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Office of Scientific & Technical Information Technical Reports

Reports, articles and other documents harvested from the Office of Scientific and Technical Information.

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  • January 31, 2009

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  • May 19, 2016, 9:45 a.m.

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  • Nov. 7, 2016, 8:15 p.m.

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Kamil, Shoaib A.; Hendry, Gilbert; Biberman, Aleksandr; Chan, Johnnie; Lee, Benjamin G.; Mohiyuddin, Marghoob et al. Analysis of Photonic Networks for a Chip Multiprocessor Using Scientific Applications, article, January 31, 2009; Berkeley, California. (digital.library.unt.edu/ark:/67531/metadc828228/: accessed December 13, 2018), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.