Dual-Side Wafer Processing and Resonant Tunneling Transistor Applications

PDF Version Also Available for Download.

Description

We describe dual-side wafer processing and its application to resonant tunneling transistors in a planar configuration. The fabrication technique utilizes a novel flip-chip, wafer thinning process called epoxy-bond and stop-etch (EBASE) process, where the substrate material is removed by selective wet etching and stopped at an etch-stop layer. This EBASE method results in a semiconductor epitaxial layer that is typically less than a micron thick and has a mirror-finish, allowing backside gates to be placed in close proximity to frontside gates. Utilizing this technique, a resonant tunneling transistor--the double electron layer tunneling transistor (DELTT)--can be fabricated in a fully planar ... continued below

Physical Description

11 p.

Creation Information

Moon, J.S.; Simmons, J.A.; Wendt, J.R.; Hietala, V.M.; Reno, J.L.; Baca, W.E. et al. July 20, 1999.

Context

This article is part of the collection entitled: Office of Scientific & Technical Information Technical Reports and was provided by UNT Libraries Government Documents Department to Digital Library, a digital repository hosted by the UNT Libraries. More information about this article can be viewed below.

Who

People and organizations associated with either the creation of this article or its content.

Sponsor

Publisher

  • Sandia National Laboratories
    Publisher Info: Sandia National Labs., Albuquerque, NM, and Livermore, CA (United States)
    Place of Publication: Albuquerque, New Mexico

Provided By

UNT Libraries Government Documents Department

Serving as both a federal and a state depository library, the UNT Libraries Government Documents Department maintains millions of items in a variety of formats. The department is a member of the FDLP Content Partnerships Program and an Affiliated Archive of the National Archives.

Contact Us

What

Descriptive information to help identify this article. Follow the links below to find similar items on the Digital Library.

Description

We describe dual-side wafer processing and its application to resonant tunneling transistors in a planar configuration. The fabrication technique utilizes a novel flip-chip, wafer thinning process called epoxy-bond and stop-etch (EBASE) process, where the substrate material is removed by selective wet etching and stopped at an etch-stop layer. This EBASE method results in a semiconductor epitaxial layer that is typically less than a micron thick and has a mirror-finish, allowing backside gates to be placed in close proximity to frontside gates. Utilizing this technique, a resonant tunneling transistor--the double electron layer tunneling transistor (DELTT)--can be fabricated in a fully planar configuration, where the tunneling between two selectively-contacted 2DEGs in GaAs or InGaAs quantum wells is modulated by surface Schottky gate. Low temperature electrical characterization yields source-drain I-V curves with a gate-tunable negative differential resistance.

Physical Description

11 p.

Notes

OSTI as DE00009577

Medium: P; Size: 11 pages

Source

  • 1999 Joint International Meeting (SOTAPOCS XXXI), Honolulu, HI (US), 10/17/1999--10/22/1999

Language

Item Type

Identifier

Unique identifying numbers for this article in the Digital Library or other systems.

  • Report No.: SAND99-1419C
  • Grant Number: AC04-94AL85000
  • Office of Scientific & Technical Information Report Number: 9577
  • Archival Resource Key: ark:/67531/metadc792359

Collections

This article is part of the following collection of related materials.

Office of Scientific & Technical Information Technical Reports

Reports, articles and other documents harvested from the Office of Scientific and Technical Information.

Office of Scientific and Technical Information (OSTI) is the Department of Energy (DOE) office that collects, preserves, and disseminates DOE-sponsored research and development (R&D) results that are the outcomes of R&D projects or other funded activities at DOE labs and facilities nationwide and grantees at universities and other institutions.

What responsibilities do I have when using this article?

When

Dates and time periods associated with this article.

Creation Date

  • July 20, 1999

Added to The UNT Digital Library

  • Dec. 19, 2015, 7:14 p.m.

Description Last Updated

  • April 6, 2017, 7:29 p.m.

Usage Statistics

When was this article last used?

Yesterday: 0
Past 30 days: 0
Total Uses: 3

Interact With This Article

Here are some suggestions for what to do next.

Start Reading

PDF Version Also Available for Download.

International Image Interoperability Framework

IIF Logo

We support the IIIF Presentation API

Moon, J.S.; Simmons, J.A.; Wendt, J.R.; Hietala, V.M.; Reno, J.L.; Baca, W.E. et al. Dual-Side Wafer Processing and Resonant Tunneling Transistor Applications, article, July 20, 1999; Albuquerque, New Mexico. (digital.library.unt.edu/ark:/67531/metadc792359/: accessed December 16, 2018), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.