Optimizing performance of superscalar codes for a single Cray X1MSP processor

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The growing gap between sustained and peak performance for full-scale complex scientific applications on conventional supercomputers is a major concern in high performance computing. The recently-released vector-based Cray X1 offers to bridge this gap for many demanding scientific applications. However, this unique architecture contains both data caches and multi-streaming processing units, and the optimal programming methodology is still under investigation. In this paper we investigate Cray X1 code optimization for a suite of computational kernels originally designed for superscalar processors. For our study, we select four applications from the SPLASH2 application suite (1-D FFT,Radix, Ocean, and Nbody), two kernels from ... continued below

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Shan, Hongzhang; Strohmaier, Erich & Oliker, Leonid June 8, 2004.

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The growing gap between sustained and peak performance for full-scale complex scientific applications on conventional supercomputers is a major concern in high performance computing. The recently-released vector-based Cray X1 offers to bridge this gap for many demanding scientific applications. However, this unique architecture contains both data caches and multi-streaming processing units, and the optimal programming methodology is still under investigation. In this paper we investigate Cray X1 code optimization for a suite of computational kernels originally designed for superscalar processors. For our study, we select four applications from the SPLASH2 application suite (1-D FFT,Radix, Ocean, and Nbody), two kernels from the NAS benchmark suite (3-DFFT and CG), and a matrix-matrix multiplication kernel. Results show that for many cases, the addition of vectorization compiler directives results faster runtimes. However, to achieve a significant performance improvement via increased vector length, it is often necessary to restructure the program at the source level sometimes leading to algorithmic level transformations. Additionally, memory bank conflicts may result in substantial performance losses. These conflicts can often be exacerbated when optimizing code for increased vector lengths, and must be explicitly minimized. Finally, we investigate the relationship of the X1 data caches on overall performance.

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  • Cray Uers Group CUG 2004, Knoxville, TN, May17-21, 2004

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  • Report No.: LBNL--55635
  • Grant Number: DE-AC02-05CH11231
  • Office of Scientific & Technical Information Report Number: 860889
  • Archival Resource Key: ark:/67531/metadc789037

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  • June 8, 2004

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  • Dec. 3, 2015, 9:30 a.m.

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  • April 1, 2016, 8:09 p.m.

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Shan, Hongzhang; Strohmaier, Erich & Oliker, Leonid. Optimizing performance of superscalar codes for a single Cray X1MSP processor, article, June 8, 2004; Berkeley, California. (digital.library.unt.edu/ark:/67531/metadc789037/: accessed October 22, 2017), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.