Evaluation of architectural paradigms for addressing theprocessor-memory gap

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Many high performance applications run well below the peak arithmetic performance of the underlying machine, with inefficiencies often attributed to poor memory system behavior. In the context of scientific computing we examine three emerging processors designed to address the well-known gap between processor and memory performance through the exploitation of data parallelism. The VIRAM architecture uses novel PIM technology to combine embedded DRAM with a vector co-processor for exploiting its large bandwidth potential. The DIVA architecture incorporates a collection of PIM chips as smart-memory coprocessors to a conventional microprocessor, and relies on superword-level parallelism to make effective use of the ... continued below

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Oliker, Leonid; Gorden, Grime; Husbands, Parry & Chame, Jacqualine July 4, 2003.

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Many high performance applications run well below the peak arithmetic performance of the underlying machine, with inefficiencies often attributed to poor memory system behavior. In the context of scientific computing we examine three emerging processors designed to address the well-known gap between processor and memory performance through the exploitation of data parallelism. The VIRAM architecture uses novel PIM technology to combine embedded DRAM with a vector co-processor for exploiting its large bandwidth potential. The DIVA architecture incorporates a collection of PIM chips as smart-memory coprocessors to a conventional microprocessor, and relies on superword-level parallelism to make effective use of the available memory bandwidth. The Imagine architecture provides a stream-aware memory hierarchy to support the tremendous processing potential of SIMD controlled VLIW clusters. First we develop a scalable synthetic probe that allows us to parametize key performance attributes of VIRAM, DIVA and Imagine while capturing the performance crossover points of these architectures. Next we present results for scientific kernels with different sets of computational characteristics and memory access patterns. Our experiments allow us to evaluate the strategies employed to exploit data parallelism, isolate the set of application characteristics best suited to each architecture and show a promising direction towards interfacing leading-edge processor technology with high-end scientific computations.

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  • Report No.: LBNL--54907
  • Grant Number: DE-AC02-05CH11231
  • DOI: 10.2172/860302 | External Link
  • Office of Scientific & Technical Information Report Number: 860302
  • Archival Resource Key: ark:/67531/metadc784866

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Office of Scientific & Technical Information Technical Reports

Reports, articles and other documents harvested from the Office of Scientific and Technical Information.

Office of Scientific and Technical Information (OSTI) is the Department of Energy (DOE) office that collects, preserves, and disseminates DOE-sponsored research and development (R&D) results that are the outcomes of R&D projects or other funded activities at DOE labs and facilities nationwide and grantees at universities and other institutions.

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  • July 4, 2003

Added to The UNT Digital Library

  • Dec. 3, 2015, 9:30 a.m.

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  • Sept. 21, 2017, 3:49 p.m.

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Oliker, Leonid; Gorden, Grime; Husbands, Parry & Chame, Jacqualine. Evaluation of architectural paradigms for addressing theprocessor-memory gap, report, July 4, 2003; Berkeley, California. (digital.library.unt.edu/ark:/67531/metadc784866/: accessed October 17, 2017), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.