A Low-Power VHDL Design for an Elliptic Curve Digital Signature Chip

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Description

The authors present a VHDL design that incorporates optimizations intended to provide digital signature generation with as little power, space, and time as possible. These three primary objectives of power, size, and speed must be balanced along with other important goals, including flexibility of the hardware and ease of use. The highest-level function doffered by their hardware design is Elliptic Curve Optimal El Gamal digital signature generation. The parameters are defined over the finite field GF(2{sup 178}), which gives security that is roughly equivalent to that provided by 1500-bit RSA signatures. The optimizations include using the point-halving algorithm for elliptic ... continued below

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28 pages

Creation Information

SCHROEPPEL, RICHARD C.; BEAVER, CHERYL L.; DRAELOS, TIMOTHY J.; GONZALES, RITA A. & MILLER, RUSSELL D. September 1, 2002.

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  • Sandia National Laboratories
    Publisher Info: Sandia National Labs., Albuquerque, NM, and Livermore, CA (United States)
    Place of Publication: Albuquerque, New Mexico

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Description

The authors present a VHDL design that incorporates optimizations intended to provide digital signature generation with as little power, space, and time as possible. These three primary objectives of power, size, and speed must be balanced along with other important goals, including flexibility of the hardware and ease of use. The highest-level function doffered by their hardware design is Elliptic Curve Optimal El Gamal digital signature generation. The parameters are defined over the finite field GF(2{sup 178}), which gives security that is roughly equivalent to that provided by 1500-bit RSA signatures. The optimizations include using the point-halving algorithm for elliptic curves, field towers to speed up the finite field arithmetic in general, and further enhancements of basic finite field arithmetic operations. The result is a synthesized VHDL digital signature design (using a CMOS 0.5{micro}m, 5V, 25 C library) of 191,000 gates that generates a signature in 4.4 ms at 20 MHz.

Physical Description

28 pages

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  • Other Information: PBD: 1 Sep 2002

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  • Report No.: SAND2002-3194
  • Grant Number: AC04-94AL85000
  • DOI: 10.2172/802030 | External Link
  • Office of Scientific & Technical Information Report Number: 802030
  • Archival Resource Key: ark:/67531/metadc742650

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Reports, articles and other documents harvested from the Office of Scientific and Technical Information.

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  • September 1, 2002

Added to The UNT Digital Library

  • Oct. 19, 2015, 7:39 p.m.

Description Last Updated

  • April 12, 2016, 4:48 p.m.

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SCHROEPPEL, RICHARD C.; BEAVER, CHERYL L.; DRAELOS, TIMOTHY J.; GONZALES, RITA A. & MILLER, RUSSELL D. A Low-Power VHDL Design for an Elliptic Curve Digital Signature Chip, report, September 1, 2002; Albuquerque, New Mexico. (digital.library.unt.edu/ark:/67531/metadc742650/: accessed January 16, 2018), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.