Testing of the TriP Chip Running at 132 nsec Using a Modified AFE Board

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In this note we describe the first set of tests done with a sample of TriP chips that were mounted on a modified AFE board. The modifications consisted of different firmware and the replacement of one power supply switch. The board used was a standard AFEIc board (red type) on which new MCMs (MCMIIs) were mounted. The new MCMs were designed to support the TriP and emulate the SVX for readout when mounted on an AFEIc board. The TriP and the MCMs are described in Ref. [1]. Two versions of the MCMII were designed and built: one (MCMIIb) supports two ... continued below

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490 Kilobytes pages

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al., Juan Estrada et December 19, 2003.

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Description

In this note we describe the first set of tests done with a sample of TriP chips that were mounted on a modified AFE board. The modifications consisted of different firmware and the replacement of one power supply switch. The board used was a standard AFEIc board (red type) on which new MCMs (MCMIIs) were mounted. The new MCMs were designed to support the TriP and emulate the SVX for readout when mounted on an AFEIc board. The TriP and the MCMs are described in Ref. [1]. Two versions of the MCMII were designed and built: one (MCMIIb) supports two TriP chips wirebonded directly to the MCM substrate. The other, (MCMIIc) supports one TriP which can be either wirebonded directly or packaged into a standard TQFP surface mount package. Due to space constraints, this MCM can support only 1 TriP. We tested 6 TriP chips on 3 different MCMIIb (MCMIIb-1, MCMIIb-2 and MCMIIb-3) and 2 other TriPs were tested on MCMIIc, one of them with an unpackaged TriP (MCMIIc-1) and the other with a packaged TriP (MCMIIc-2). A set of 10 programable internal registers control the TriP operation, the description of these registers can be found in [1]. Table 1 shows the values used for the tests described in this note. In Ref. [1] there is a description of the signals that are needed to operate the TriP chip. We implemented in a Field Programable Gate Array (FPGA), also part of the MCM, a set of shift registers that allow us to download via the 1553 interface to the AFE board, any desired timing for the signals that the FPGA has to send to the TriP chip. These registers are run with a 121.21 MHz clock (which is 16x the crossing clock and phase locked to it), which means that each bit corresponds to a time interval of 8.25 nsec. Finer control of timing is possible, but this changing the programing of the FPGA and recompiling. The bits downloaded to these shift registers inside the TriP are listed in Table 2.

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490 Kilobytes pages

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  • Other Information: PBD: 19 Dec 2003

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  • Report No.: FERMILAB-TM-2227
  • Grant Number: AC02-76CH03000
  • DOI: 10.2172/820409 | External Link
  • Office of Scientific & Technical Information Report Number: 820409
  • Archival Resource Key: ark:/67531/metadc739143

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  • December 19, 2003

Added to The UNT Digital Library

  • Oct. 18, 2015, 6:40 p.m.

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  • April 1, 2016, 5:05 p.m.

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al., Juan Estrada et. Testing of the TriP Chip Running at 132 nsec Using a Modified AFE Board, report, December 19, 2003; Batavia, Illinois. (digital.library.unt.edu/ark:/67531/metadc739143/: accessed June 24, 2018), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.